1. A unified signal transition graph model for asynchronous control circuit synthesis

   • Alexandre Yakovlev
   • Luciano Lavagno
   • Alberto Sangiovanni-Vincentelli

   OriginalPaper Pages: 139 - 188

2. On the models for asynchronous circuit behaviour with OR causality

   • Alexandre Yakovlev
   • Michael Kishinevsky
   • Marta Pietkiewicz-Koutny

   OriginalPaper Pages: 189 - 233

3. The incorporation of testing into formal verification: Direct, modular, and hierarchical correctness degrees

   • Leo Marcus

   OriginalPaper Pages: 235 - 261

4. Regrouping parallel processes

   • T. Bolognesi

   OriginalPaper Pages: 263 - 302

5. Call for papers

   Announcement Pages: i - ii