A 16 × 16 Cellular Neural Network Universal Chip: The First Complete Single-Chip Dynamic Computer Array with Distributed Memory and with Gray-Scale Input-Output J. M. CruzL. O. Chua OriginalPaper Pages: 227 - 237
A 6 × 6 Cells Interconnection-Oriented Programmable Chip for CNN Mario SalernoFausto SargeniVincenzo Bonaiuto OriginalPaper Pages: 239 - 250
Analog VLSI Design Constraints of Programmable Cellular Neural Networks Peter KingetMichiel Steyaert OriginalPaper Pages: 251 - 262
Focal-Plane and Multiple Chip VLSI Approaches to CNNs M. AnguitaF. J. PelayoA. Prieto OriginalPaper Pages: 263 - 275
Architecture and Design of 1-D Enhanced Cellular Neural Network Processors for Signal Detection Michelle Y. WangBing J. SheuAustin K. Cho OriginalPaper Pages: 277 - 290
Analog VLSI Circuits for Competitive Learning Networks H. C. CardD. K. McNeillC. R. Schneider OriginalPaper Pages: 291 - 314
Design of Neural Networks Based on Wave-Parallel Computing Technique Yasushi YuminakaYoshisato SasakiTatsuo Higuchi OriginalPaper Pages: 315 - 327