Skip to main content
SpringerLink
Log in

Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications

  • Published:
Journal of Electronic Materials Aims and scope Submit manuscript

Abstract

Dual-metal junctionless nanotube field-effect transistors (DMJN-TFETs) for improvised analog and digital applications are described. It has been realized that, compared with existing junctionless nanowire FETs, in particular, junctionless-gate all around (J-GAA) metal oxide semiconductors (MOS) FETs, dual-metal junctionless-gate all around (DMJ-GAA) MOSFETs, and junctionless nanotube (JN) FETs, DMJN-TFET MOSFETs exhibit higher Ids, gm, gd and fT compared with the JNFETs, making it a favorable device for high-frequency analog FET applications. DMJN TFETs exhibit a surpassing ION/IOFF ratio, with the subthreshold slope approaching the ideal values, a mitigated device channel resistance (Rch), advanced early voltage (VEA), a higher transconductance generation factor, maximum transducer power gain, unilateral power gain, and minimized noise conductivity and noise figure. Also, the small signal metrics including the transmission coefficients (S21 and S12) and reflection coefficients (S11 and S22) have been investigated to authenticate the small signal conduct of our device. These improvised characteristics make a DMJN-TFET the most suitable device design for both digital and analog applications employing FETs.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Similar content being viewed by others

References

  1. The National Technology Roadmap for Semiconductor Technology Needs. San Jose, CA: Semiconductor Industry Assoc., 1997.

  2. Y. Taur and T.H. Ning, Fundamentals of Modern VLSI Devices, 2nd ed. (Cambridge: Cambridge University Press, 1998), pp. 24–45.

    Google Scholar 

  3. T. Sekigawa and Y. Hayashi, Solid State Electron. 27, 827 (1984).

    Article  Google Scholar 

  4. R.H. Yan, A. Ourmazd, and K.F. Lee, IEEE Trans. Electron Devices 39, 1704 (1992).

    Article  CAS  Google Scholar 

  5. D. Frank, S. E. Laux, and M. V. Fischett, IEDM Tech. Dig. 553 (1992).

  6. S. Saurabh and M.J. Kumar, Fundamentals of Tunnel Field-Effect Transistors (Boca Raton: CRC, 2016).

    Book  Google Scholar 

  7. M.J. Kumar, R. Vishnoi, and P. Pandey, Tunnel Field-effect Transistors (TFET): Modelling and Simulation, 1st ed. (London: Wiley, 2016), pp. 12–40.

    Google Scholar 

  8. K.J. Kuhn, Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59, 1813 (2012).

    Article  CAS  Google Scholar 

  9. M. Li, Proc. VLSI Tech. Symp. 6, 94 (2009).

    Google Scholar 

  10. N. Singh, IEDM Tech. Dig. 12, 548 (2006).

    Google Scholar 

  11. S. Bangsaruntip, IEDM Tech. Dig. 12, 297 (2009).

    Google Scholar 

  12. J. Fan, M. Li, X. Xu, Y. Yang, H. Xuan, and R. Huang, IEEE Trans. Electron Devices 62, 213 (2015).

    Article  CAS  Google Scholar 

  13. J. Hur, IEEE Electron Device Lett. 37, 541 (2016).

    Article  CAS  Google Scholar 

  14. S. Sahay and M.J. Kumar, IEEE Trans. Electron Devices 63, 5055 (2016).

    Article  Google Scholar 

  15. S. Sahay and M.J. Kumar, IEEE Trans. Electron Devices 63, 4138 (2016).

    Article  CAS  Google Scholar 

  16. S. Sahay and M.J. Kumar, IEEE Trans. Electron Devices 64, 1330 (2017).

    Article  Google Scholar 

  17. S. Sahay and M.J. Kumar, IEEE Trans. Electron Devices 63, 3790 (2016).

    Article  CAS  Google Scholar 

  18. S. Sahay and M.J. Kumar, IEEE Trans. Electron Devices 64, 1851 (2017).

    Article  Google Scholar 

  19. V. Nathan and N.C. Das, IEEE Trans. Electron Devices 40, 1888 (1993).

    Article  CAS  Google Scholar 

  20. T. Hoffmann, IEDM Tech. Dig. 725 (2005).

  21. H.M. Fahad, C.E. Smith, J.P. Rojas, and M.M. Hussain, Nano Lett. 11, 4393 (2011).

    Article  CAS  Google Scholar 

  22. H.M. Fahad and M.M. Hussain, Sci. Rep. 2, 475 (2012).

    Article  Google Scholar 

  23. D. Tekleab, H. H. Tran, J. W. Sleight, and D. Chidambarrao, U.S. Patent 0 217 468 (2012).

  24. D. Tekleab, IEEE Electron Device Lett. 35, 506 (2014).

    Article  CAS  Google Scholar 

  25. A.N. Hanna, H.M. Fahad, and M.M. Hussain, Sci. Rep. 9, 9843 (2015).

    Article  Google Scholar 

  26. H.M. Fahad and M.M. Hussain, IEEE Trans. Electron Devices 60, 1034 (2013).

    Article  CAS  Google Scholar 

  27. A.N. Hanna and M.M. Hussain, J. Appl. Phys. 117, 014310 (2015).

    Article  Google Scholar 

  28. J.-P. Colinge, C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, Nat. Nanotechnol. 5, 225 (2010).

    Article  CAS  Google Scholar 

  29. A. Goel, S. Rewari, S. Verma, and R.S. Gupta, Microsyst. Technol. 26, 1697 (2020).

    Article  Google Scholar 

  30. S. Rewari, S. Haldar, V. Nath, S.S. Deswal, and R.S. Gupta, Superlattices Microstruct. J. 90, 8 (2016).

    Article  CAS  Google Scholar 

  31. A. Goel, S. Rewari, S. Verma, and R.S. Gupta, Science 66, 2437 (2019).

    CAS  Google Scholar 

  32. C.-W. Lee, A. Afzalian, N.D. Akhavan, R. Yan, I. Ferain, and J.P. Colinge, Appl. Phys. Lett. 94, 053511 (2009).

    Article  Google Scholar 

  33. J.C. Pravin, D. Nirmal, P. Prajoon, and J. Ajayan, Physica E 83, 95 (2016).

    Article  Google Scholar 

  34. H. Lou, L. Zhang, Y. Zhu, X. Lin, S. Yang, J. He, and M. Chan, IEEE Trans. Electron Devices 59, 1826 (2012).

    Article  Google Scholar 

  35. ATLAS: 3D Device Simulator, SILVACO International, 2016.

  36. R. Lin, Q. Lu, P. Ranade, T.J. King, and C. Hu, IEEE Electron Dev. Lett. 23, 49 (2002).

    Article  Google Scholar 

  37. J. Fan, M. Li, X. Xu, Y. Yang, H. Xuan, and R. Hang, IEEE Trans. Electron Dev. 62, 213 (2015).

    Article  CAS  Google Scholar 

  38. H. Cheng, S. Uno, and K. Nakazato, J. Comput. Electron. 14, 321 (2015).

    Article  CAS  Google Scholar 

  39. G. Timp, IEDM Tech. Dig. 55 (1999).

  40. A. Tsormpatzoglou, D. H. Tassis, C. A. Dimitriadis, G. Ghibaudo, G. Pananakakis, and R. Clerc, Semicond. Sci. Technol. 24075017 (2009).

  41. E. Gnani, S. Reggiani, M. Rudan, and G. Baccarani, IEEE Trans. Nanotechnol. 6, 90 (2007).

    Article  Google Scholar 

  42. S. Datta, F. Assad, and M.S. Lundstrom, The silicon MOSFET from a transmission viewpoint. Superlattices Microstruct. 23, 771–780 (1998).

    Article  CAS  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronics and Communication Engineering, Maharaja Agrasen Institute of Technology, GGSIPU, New Delhi, India

    Anubha Goel & R. S. Gupta

  2. Department of Electronics and Communication Engineering, Delhi Technical University, New Delhi, India

    Sonam Rewari

  3. Department of Electronics, Banasthali Vidyapith, Niwai, Banasthali, Rajasthan, 304022, India

    Seema Verma

Authors
  1. Anubha Goel
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Sonam Rewari
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Seema Verma
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. R. S. Gupta
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Anubha Goel.

Ethics declarations

Conflict of interest

The authors declare that they have no conflict of interest.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Goel, A., Rewari, S., Verma, S. et al. Novel Dual-Metal Junctionless Nanotube Field-Effect Transistors for Improved Analog and Low-Noise Applications. J. Electron. Mater. 50, 108–119 (2021). https://doi.org/10.1007/s11664-020-08541-9

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11664-020-08541-9

Keywords

Search

Navigation