Skip to main content
SpringerLink
Log in

In-order delivery approach for 2D and 3D NoCs

  • Published:
The Journal of Supercomputing Aims and scope Submit manuscript

Abstract

In many applications, it is critical to guarantee the in-order delivery of requests from the master cores to the slave cores, so that the requests can be executed in the correct order without requiring buffers. Since in NoCs packets may use different paths and on the other hand traffic congestion varies on different routes, the in-order delivery constraint cannot be met without support. To guarantee the in-order delivery, traditional approaches either use dimension-order routing or employ reordering buffers at network interfaces. Dimension-order routing degrades the performance considerably while the usage of reordering buffers imposes large area overhead. In this paper, we present a mechanism allowing packets to be routed through multiple paths in the network, helping to balance the traffic load while guaranteeing the in-order delivery. The proposed method combines the advantages of both deterministic and adaptive routing algorithms. The simple idea is to use different deterministic algorithms for independent flows. This approach neither requires reordering buffers nor limits packets to use a single path. The algorithm is simple and practical with negligible area overhead over dimension-order routing. The concept is investigated in both 2D and 3D mesh networks.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11
Fig. 12
Fig. 13
Fig. 14
Fig. 15
Fig. 16
Fig. 17

Similar content being viewed by others

References

  1. Palesi M, Daneshtalab M (2014) Routing algorithms in networks-on-chip. Springer, Berlin

    Book  Google Scholar 

  2. Pavlidis VF, Friedman EG (2007) 3-D topologies for networks-on-chip. IEEE Trans Very Large Scale Integr VLSI Syst 15(10):1081–1090

    Article  Google Scholar 

  3. Mubeen S, Kumar S (2010) Designing efficient source routing for mesh topology network on chip platforms. In: Proceedings of the 13th euromicro conference on digital system design: architectures, methods and tools, 2010, pp 181–188

  4. Daneshtalab M, Ebrahimi M, Liljeberg P, Plosila J, Tenhunen H (2010) Input–output selection based router for networks-on-chip. In: IEEE computer society annual symposium on VLSI (ISVLSI), 2010, pp 92–97

  5. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2011) Agent-based on-chip network using efficient selection method. In: Proceedings of 19th IFIP/IEEE international conference on very large scale integration (VLSI-SoC), 2011, pp 284–289

  6. Wang X, Mak T, Yingtao Jiang MY, Daneshtalab M, Palesi M (2013) On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. In: Proceedings of seventh IEEE/ACM international symposium on networks on chip (NoCS), 2013, pp 1–8

  7. Murali S, Atienza D, Benini L, De Micheli G (2007) A method for routing packets across multiple paths in NoCs with in-order delivery and fault-tolerance gaurantees. VLSI Des 1–11. doi:10.1155/2007/37627

  8. Ebrahimi M, Jahangireyan A (2013) Aerodynamic optimization of airfoils using adaptive parameterization and genetic algorithm. J Optim Theory Appl 162:257–271

  9. Wang X, Yang M, Jiang Y, Mak T, Daneshtalab M, Palesi M (2014) On self-tuning networks-on-chip for dynamic network-flow dominance adaptation. ACM Trans Embed Comput Syst (TECS) 13(2):73–94

    Google Scholar 

  10. Li M, Zeng Q-A, Jone W-B (2006) DyXY—a proximity congestion-aware deadlock-free dynamic routing method for network on chip. In: Proceedings of 43rd ACM/IEEE design automation conference, 2006, pp 849–852

  11. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Tenhunen H (2011) Exploring partitioning methods for 3D networks-on-chip utilizing adaptive routing model. In: Proceedings of the fifth ACM/IEEE international symposium on networks-on-chip, 2011, pp 73–80

  12. Ebrahimi M, Daneshtalab M, Liljeberg P, Plosila J, Flich J, Tenhunen H (2012) Path-based partitioning methods for 3D networks-on-chip with minimal adaptive routing. IEEE Trans Comput 63:718–733

  13. Palesi M, Holsmark R, Wang X, Kumar S, Yang M, Jiang Y, Catania V (2010) An efficient technique for in-order packet delivery with adaptive routing algorithms in networks on chip. In: Proceedings of the 13th euromicro conference on digital system design: architectures, methods and tools, 2010, pp 37–44

  14. Devadas S, Cho MH, Shim KS, Lis M (2009) Guaranteed in-order packet delivery using exclusive dynamic virtual channel allocation, Technical Report, CSAIR-TR-2009-036, August 2009. Massachusetts Institute of Technology

  15. Lis M, Cho MH, Shim KS, Devadas S (2010) Path-diverse in-order routing. In: Proceedings of international conference on green circuits and systems (ICGCS), 2010, pp 311–316

  16. Ebrahimi M, Daneshtalab M, Plosila J (2013) In-order delivery approach for 3D NoCs. In: Proceedings of 17th CSI international symposium on computer architecture & digital systems (CADS), pp 93–98

  17. Wang H-S, Zhu X, Peh L-S, Malik S (2002) Orion: a power-performance simulator for interconnection networks. In: Proceedings of 35th annual IEEE/ACM international symposium on microarchitecture (MICRO), 2002, pp 294–305

  18. Ebrahimi M, Tenhunen H, Dehyadegari M (2013) Fuzzy-based adaptive routing algorithm for networks-on-chip. J Syst Archit 59(7):516–527

    Article  Google Scholar 

  19. Tol EBVD, Jaspers EGT (2002) Mapping of MPEG-4 decoding on a flexible architecture platform. In: Proceedings of media processors, 2002, pp 1–13

  20. Martin MMK, Sorin DJ, Beckmann BM, Marty MR, Xu M, Alameldeen AR, Moore KE, Hill MD, Wood DA (2005) Multifacet’s general execution-driven multiprocessor simulator (GEMS) toolset. SIGARCH Comput Arch News 33(4):92–99

    Article  Google Scholar 

  21. Woo SC, Ohara M, Torrie E, Singh JP, Gupta A (1995) The SPLASH-2 programs: characterization and methodological considerations. In: Proceedings of 22nd annual international symposium on computer architecture, 1995, pp 24–36

  22. Muralimanohar N, Balasubramonian R, Jouppi N (2007) Optimizing NUCA organizations and wiring alternatives for large caches with CACTI 6.0. In: Proceedings of the 40th annual IEEE/ACM international symposium on microarchitecture, 2007, pp 3–14

  23. Park D, Eachempati S, Das R, Mishra AK, Xie Y, Vijaykrishnan N, Das CR (2008) MIRA: a multi-layered on-chip interconnect router architecture. In: Proceedings of international symposium on computer architecture, 2008, pp 251–261

  24. Beckmann BM, Wood DA (2004) Managing wire delay in large chip-multiprocessor caches. In: Proceedings of the 37th annual IEEE/ACM international symposium on microarchitecture, 2004, pp 319–330

Download references

Acknowledgments

This work was supported by VINNOVA (Swedish Agency for Innovation Systems) within the CUBRIC and ERoT projects and by Academy of Finland.

Author information

Authors and Affiliations

  1. University of Turku, Turku, Finland

    Masoud Daneshtalab, Masoumeh Ebrahimi, Sergei Dytckov & Juha Plosila

  2. KTH Royal Institute of Technology, Stockholm, Sweden

    Masoud Daneshtalab & Masoumeh Ebrahimi

Authors
  1. Masoud Daneshtalab
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Masoumeh Ebrahimi
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Sergei Dytckov
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. Juha Plosila
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Masoumeh Ebrahimi.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Daneshtalab, M., Ebrahimi, M., Dytckov, S. et al. In-order delivery approach for 2D and 3D NoCs. J Supercomput 71, 2877–2899 (2015). https://doi.org/10.1007/s11227-014-1339-y

Download citation

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11227-014-1339-y

Keywords

Search

Navigation