Abstract
Time difference amplifier (TDA) is often used in time domain interconnection, computing and measurement. Gain and linearity control are two main design issues. To reduce the nonlinear distortion, a novel self-adaptive pulse shrink circuit is proposed for the SR-latch based time difference amplifier. The multi-stage self-adaptive pulse shrink unit can compensate for the gain error caused by the high-order items and decrease the linearity problem. A programmable gain control circuit is also proposed to improve the gain range of the TDA. The proposed TDA including gain reconfiguration and linearity control is implemented by using SMIC 40nm CMOS technology. Post layout simulation demonstrates that the proposed TDA achieves from 8 to 100 s/s programmable gain within the input linear range \([-36\,\hbox {ps},36\,\hbox {ps}]\). The total area is \(21.186\,\upmu \hbox {m} \times 18.435\,\upmu \hbox {m}\). The total power consumption is \(31.45\,\upmu \hbox {W}\) when the gain is 10 and the toggle frequency is 100 MHz.
Similar content being viewed by others
References
Sayal, A., Fathima, S., Nibhanupudi, S. S. T., & Kulkarni, J. P. (2019). 14.4 All-digital time-domain CNN engine using bidirectional memory delay lines for energy-efficient edge computing. In IEEE international solid-state circuits conference (ISSCC) (pp. 228–230).
Wang, W., & Buckwalter, J. F. (2016). Source coding and preemphasis for double-edged pulsewidth modulation serial communication. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 24(2), 555–566.
Henzler, S. (2010). Time-to-digital converter basics. Time-to-digital converters (pp. 5–18). Dordrecht: Springer.
Long, X., Wang, Q., Jiang, J., & Guan, N. (2017). An on-chip circuit for timing measurement of SRAM IP. In 2017 IEEE 12th international conference on ASIC (ASICON) (pp. 569–572).
Kim, K. S., Kim, Y. H., Yu, W., & Cho, S. H. (2013). A 7 bit, 3.75 ps resolution two-step time-to-digital converter in 65 nm CMOS using pulse-train time amplifier. IEEE Journal of Solid-State Circuits, 48(4), 1009–1017.
Shingo, M., Tetsuya, I., Toru, N., Makoto, I., & Kunihiro, A. (2010). Time-to-digital converter based on time difference amplifier with non-linearity calibration. In European conference on IEEE solid-state circuits (ESSCIRC) (pp. 266–269).
Shingo, M., Toru, N., Makoto, I., & Kunihiro, A. (2010). Cascaded time difference amplifier with differential logic delay cell. In Proceedings of the 15th Asia South Pacific design automation conference (pp. 355–356).
Chiu, P., Liu, M., Tang, Q., & Kim, C. H. (2018). A 2.1 pJ/bit, 8 Gb/s ultra-low power in-package serial link featuring a time-based front-end and a digital equalizer. In 2018 IEEE Asian solid-state circuits conference (A-SSCC) (pp. 187–190).
Abas, A. M., Bystrov, A., Kinniment, D. J., Maevsky, O. V., Russell, G., & Yakovlev, A. V. (2002). Time difference amplifier. Electronics Letters, 38(23), 1437–1438.
Lee, M., & Abidi, A. A. (2008). A 9 b, 1.25 ps resolution coarse-fine time-to-digital converter in 90 nm CMOS that amplifies a time residue. IEEE Journal of Solid-State Circuits, 43(4), 769–777.
Wu, W., Baker, R. J., Bikkina, P., Long, Y., Levy, A., & Mikkola, E. (2018). Design and analysis of a feedback time difference amplifier with linear and programmable gain. IEEE Analog Integrated Circuits and Signal Processing, 94, 357–367.
Kinniment, D. J., Bystrov, A., & Yakovlev, A. V. (2002). Synchronization circuit performance. IEEE Journal of Solid-State Circuits, 37(2), 202–209.
Tisa, S., Lotito, A., Giudice, A., & Zappa, F. (2003). Monolithic time-to-digital converter with 20ps resolution. In European Conference on IEEE Solid-State Circuits (ESSCIRC) (pp. 465–468).
Chen, P., Liu, S. L., & Wu, J. (2000). A CMOS pulse-shrinking delay element for time interval measurement. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 47(9), 954–958.
Chen, C. C., Hwang, C. S., Lin, Y., & Liu, K. C. (2015). Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters. Review of Scientific Instruments, 86(12), 126113.
Kim, S. J., & Cho, S. H. (2009). A variation tolerent reconfigurable time difference amplifier. In International SoC design conference (ISOCC) (pp. 301–304).
Mandai, S., Nakura, T., Ikeda, M., & Asada, K. (2009). Cascaded time difference amplifier using differential logic delay cell. International SoC Design Conference (ISOCC) (pp. 194–197).
Kim, B., Kim, H., & Kim, C. H. (2015). An 8 bit, 2.6 ps two-step TDC in 65 nm CMOS employing a switched ring-oscillator based time amplifier. In IEEE custom integrated circuits conference.
Kim, K., Kim, Y., Yu, W., & Cho, S. (2012). A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier. In 2012 symposium on VLSI circuits (VLSIC) (pp. 192–193).
Kwon, H., Lee, J., Sim, J., & Park, H. (2011). A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio. In IEEE Asian solid-state circuits conference (pp. 325–328).
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Li, J., Jiang, J., Wang, Q. et al. A gain reconfigurable time difference amplifier with self-adaptive linearity control. Analog Integr Circ Sig Process 107, 435–449 (2021). https://doi.org/10.1007/s10470-020-01739-1
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-020-01739-1