Abstract
In this Letter, 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction is proposed. A reference spur is occurred by updating DCO control code at every reference clock period. To reduce a reference spur component, the phase detector which transfers phase error information only when phase error is detected has been designed. The measured clock jitter is 2.528 psrms at 1.5 GHz operation, and 3.991 psrms at 400 MHz operation. The ADPLL occupies 0.088 mm2, and consumes 1.19 mW at 1.5 GHz. This ADPLL is implemented in 65 nm CMOS technology.
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Acknowledgments
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (No. 2011-0020128); fabrication was supported by the MPW of IDEC.
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Song, J., Hwang, S., Kim, TC. et al. A 400 MHz–1.5 GHz all digital integer-N PLL with a reference spur reduction technique. Analog Integr Circ Sig Process 79, 183–189 (2014). https://doi.org/10.1007/s10470-014-0258-4
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DOI: https://doi.org/10.1007/s10470-014-0258-4