Multiplexer-based High-speed S-box Architecture for PRESENT Cipher in FPGA

Abstract

The Internet of Things (IoT) is the technology that will revolutionize our world. It is a system of interrelated devices linked to the Internet. It comprises large number of resource-constrained devices, machines and sensors. Actualization of IoT requires large amount of devices like sensors and actuators which requires large power but with bounded power supply and area. The aim of lightweight cryptography is to provide security solution for resource-constrained devices. The conventional cryptography algorithms are slow, less responsive and require more energy and storage space as compared to lightweight algorithm. Therefore, researchers are more oriented toward lightweight-based algorithms. This chapter discusses hardware implementation of PRESENT cipher on a field-programmable gate array (FPGA) platform. In this work, our goal is to improve its performance in terms of speed and minimize its area as much as possible. In our proposed design, we have implemented a combinational S-box through multiplexers and some logic gates. In this chapter, various platforms for implementation such as Spartan-6, Virtex-5 and Virtex-4 are used, and as a result, it achieves high throughput per slice for PRESENT cipher as well as highest maximum frequency.