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Challenges in Design of Very High-Speed Data Acquisition System for High-Altitude Application

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Advances in Small Satellite Technologies

Abstract

This paper chronicles the design of a very high-speed data acquisition system (DAS) which is qualified with a novel architecture for high-altitude applications. The state-of-the-art system is realized with DDR SDRAM modules as the storage media and the controller are designed with AX2000 FPGAs from Microsemi. The design of this high-altitude system matches the reliability requirements using system-level methodologies. The main features of the data acquisition system are the capability to acquire and retrieve up to 12,000 pulses with variable real-time programmable pre-pulse and post-pulse data. The system has modular design approach. Some of the main design challenges are highlighted here.

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References

  1. Scheick LZ, Swift GM, Guertin SM (2001) SEU evaluation of SRAM memories for space applications. IEEE Trans Nucl Sci 47

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  2. Micron DDR SDRAM MT46V64M16 datasheet

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  3. Axcelerator Family FPGAs datasheet

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  4. Timing Analysis of RTAX-S/SL/DSP Design Using Libero IDE v9.2, Microsemi

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Acknowledgements

The design and implementation of the contents of this paper was carried out by the M/s Centum Electronics, Bengaluru, along with DLRL, Hyderabad.

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Correspondence to S. Amruth Kumar .

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Srikar, M.S.P. et al. (2020). Challenges in Design of Very High-Speed Data Acquisition System for High-Altitude Application. In: Sastry, P.S., CV, J., Raghavamurthy, D., Rao, S.S. (eds) Advances in Small Satellite Technologies. Lecture Notes in Mechanical Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-15-1724-2_43

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  • DOI: https://doi.org/10.1007/978-981-15-1724-2_43

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-15-1723-5

  • Online ISBN: 978-981-15-1724-2

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