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Invasive Tightly Coupled Processor Arrays

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Invasive Tightly Coupled Processor Arrays

Part of the book series: Computer Architecture and Design Methodologies ((CADM))

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Abstract

In this chapter, after introducing the principles of invasive computing and a considered multi-processor system-on-a-chip (MPSoC) architecture, we dig into deeper details by introducing Tightly Coupled Processor Arrays (TCPAs), a class of coarse-grained reconfigurable processor arrays. After briefly explaining our loop mapping methodology on such architectures, we make the following contributions for realising invasive computing concepts on TCPAs: (a) development of ultra fast, distributed, and hardware-based resource invasion strategies to acquire regions of Processing Elements (PEs) of different shapes and sizes. (b) Proposing two different design variants for realising invasion strategies at the hardware level, and evaluate their timing overheads as well as hardware costs. (c) Investigation of different signalling concepts and data structure to collect information about the number and the location of invaded PEs. (d) Development of the hardware/software interfaces for integrating TCPAs into a tiled architecture, and finally, (e) evaluation of the hardware costs and timing overheads based on prototype implementations on the basis of FPGA hardware

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Notes

  1. 1.

    http://www.invasic.de.

  2. 2.

    By default, a claim may be used exclusively by the invading application. This is the implication of the term invasive computing. Through invasion, an application may isolate itself from other application which allows to provide and enforce predictability in many non-functional aspects of program execution.

  3. 3.

    This conception goes back to the notion of a “servlet”, which is a (Java) application program snippet target for execution within a web server.

  4. 4.

    Safety integrity levels are defined based on the Probability of Failures per Hour (PFH), namely, SIL 1: PFH = \(10^-5 \ldots 10^-6\); SIL 2: PFH = \(10^-6\ldots 10^-7\); SIL 3: PFH = \(10^-7\ldots 10^-8\); SIL 4: PFH = \(10^-8\ldots 10^-9\).

  5. 5.

    We assume w. l. o. g. that we start from a UDA, as any linear dependence algorithm may be systematically transformed into a UDA using localisation, see, e.g., [25, 26].

  6. 6.

    Note that \(\pi \) may be often chosen smaller than the latency \(L_l\) of one loop iteration. In that case, the execution of multiple iterations does overlap (also called modulo scheduling).

  7. 7.

    There could be another flavour of implementation by invading the first column and sending horizontal invades by PEs in the first column. However w. l. o. g., in this book, we only describe the first flavour for the sake of simplicity.

  8. 8.

    There might be other parameters such as inequality operators over the number of invaded PEs, e.g., minimum, maximum, or exact number of PEs to be invaded by invasion operands. The explanation of such parameters are w. l. o. g. excluded from this book for the sake of simplicity.

  9. 9.

    Here the order of the directions defines the direction priority at which invade signals are propagated. Without loss of generality and for the sake of simplicity in the rest of this book, we consider the horizontal direction to have higher priority, as may be observed in Fig. 2.6. Therefore, combinations such as north–west or south–west are not considered.

  10. 10.

    The use of such turn-points and their effects on the power consumption of TCPAs is discussed in Chap. 3 but in order to keep the size of invasion commands as small as possible, this feature is excluded from the explanations given in this chapter.

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    Vahid Lari

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Lari, V. (2016). Invasive Tightly Coupled Processor Arrays. In: Invasive Tightly Coupled Processor Arrays. Computer Architecture and Design Methodologies. Springer, Singapore. https://doi.org/10.1007/978-981-10-1058-3_2

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