Abstract
With highly scaled 40 or 30 nm technologies, the memory capacity increases to as much as 32 Gbit as shown in Fig. 18.1. By using gigabit-capacity NAND flash memories, SSD, Solid-State Drive that uses NAND as a mass storage of personal computers and enterprise servers is expected as a next killer application of NAND Flash memories.
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References
K. Takeuchi, “NAND successful as a media for SSD”, ISSCC, Tutorial T7, 2008.
K. Takeuchi, “Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30nm Low-Power High-Speed Solid-State Drives (SSD)”, Symposium on VLSI Circuits Tech. Dig., pp.124–125, 2008.
K. Takeuchi, “Novel Co-design of NAND Flash Memory and NAND Flash Controller Circuits for sub-30nm Low-Power High-Speed Solid-State Drives (SSD),” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, pp. 1227–1234, April 2009.
K. Ishida, et. al., “A 1.8V 30nJ Adaptive Program-Voltage (20V) Generator for 3D-Integrated NAND Flash SSD,” ISSCC Tech. Dig., pp. 238–239, 2009.
C. Park, et. al., “A High Performance Controller for NAND Flash-Based Solid State Disk (NSSD)”, NVSMW Tech. Dig., pp.17–20, 2006.
Y. Li, et. al., “A 16Gb 3b/cell NAND Flash Memory in 56nm with 8MB/s Write Rate”, ISSCC Tech. Dig., pp.506–507, 2008.
N. Shibata, et. al., “A 70nm 16Gb 16-level-cell NAND Flash Memory”, Symposium on VLSI Circuits Tech. Dig., pp.190–191, 2007.
K. Takeuchi, et al., “A 56nm CMOS 99mm2 8Gbit Multi-level NAND Flash Memory with 10Mbyte/sec Program Throughput”, IEEE Journal of Solid-State Circuits, vol. 42, pp.219–232, 2007.
T. Tanaka, et. al., “A Quick Intelligent Program Architecture for 3V-Only NAND EEPROMs”, Symposium on VLSI Circuits Tech. Dig., pp.20–21, 1992.
K. Takeuchi, et al., “A Multipage Cell Architecture for High-Speed Programming Multilevel NAND Flash Memories”, Symposium on VLSI Circuits Tech. Dig., pp. 67–68, 1997.
T. Hara, et. al., “A 146mm2 8Gb NAND Flash Memory with 70nm COMS Technology”, ISSCC Tech. Dig., pp.44–45, 2005.
K. D. Suh, et. al., “A 3.3V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme”, ISSCC Tech. Dig., pp.128–129, 1995.
K. Takeuchi, et. al., “A Source-line Programming Scheme for Low Voltage Operation NAND Flash Memories”, Symposium on VLSI Circuits Tech. Dig., pp. 37–38, 1999.
K. Takeuchi, et. al., “A Double-Level-Vth Select Gate Array Architecture for Multilevel NAND Flash Memories”, Symposium on VLSI Circuits Tech. Dig., pp. 69–70, 1995.
R. Sundaram et al., “A 128Mb NOR Flash Memory with 3MB/s Program Time and Low-Power Write Using an In-Package Inductor Chrage-Pump,” ISSCC Dig. Tech. Papers, pp. 50–51, 2005.
K. Takeuchi et al., “A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput,” ISSCC Dig. Tech. Papers, pp. 144–145, 2006.
K. Kanda, et al., “A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology,” ISSCC Dig. Tech. Papers, pp.430–431, 2008.
T. Tanzawa and T. Tanaka, “A Stable Programming Pulse Generator for Single Power Supply Flash Memories,” IEEE Journal of Solid-State Circuits, vol.32, no. 6, pp.845–851, 1997.
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Takeuchi, K. (2010). Low power 3D-integrated SSD. In: Inside NAND Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9431-5_18
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DOI: https://doi.org/10.1007/978-90-481-9431-5_18
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