Abstract
Content-addressable memories (CAMs) differentiate themselves from other memories as information is accessed by data instead of physical location. This makes CAMs popular in high-speed hardware-based search operations, such as look-up tables, data compression, image processing, register renaming, look-up buffers, and as highly associative caches in processors. However, using CAMs in systems efficiently is a challenge due to its high area cost and power dissipation. Since the parallel search operation is performed in the memory, optimization of speed and energy per search is crucial for an efficient CAM architecture. Another challenge for CAMs is the increasing leakage with every new technology node. Therefore, minimization of area and power consumption of CAMs for processor-based SoCs becomes an important design challenge.
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References
Supreet Jeloka, Naveen Akesh, Dennis Sylvester, and David Blaauw. A configurable TCAM/BCAM/SRAM using 28nm push-rule 6T bit cell. In VLSI Circuits (VLSI Circuits), 2015 Symposium on, pages C272–C273. IEEE, 2015.
Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, and Takehiko Hojo. A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 IEEE International, pages 236–237. IEEE, 2014.
Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Shyh-Jye Jou, and Ching-Te Chuang. Single-ended subthreshold SRAM with asymmetrical write/read-assist. IEEE Transactions on Circuits and Systems I: Regular Papers, 57(12):3039–3047, 2010.
Richard F Hobson. A new single-ended SRAM cell with write-assist. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(2):173–181, 2007.
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. 1.56 GHz/0.9 V energy-efficient reconfigurable CAM/SRAM using 6T-CMOS bitcell. In ESSCIRC 2017-43rd IEEE European Solid State Circuits Conference, pages 316–319. IEEE, 2017.
Greg Burda, Yesh Kolla, Jim Dieffenderfer, and Fadi Hamdan. A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file. In Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 IEEE International, pages 286–287. IEEE, 2010.
Xilinx. XA Zynq-7000 All Programmable SoC First Generation Architecture. www.xilinx.com
Jishen Zhao, Cong Xu, and Yuan Xie. Bandwidth-aware reconfigurable cache design with hybrid memory technologies. In Proceedings of the International Conference on Computer-Aided Design, pages 48–55. IEEE Press, 2011.
AD Santana Gil, FJ Quiles Latorre, M Hernandez Calvino, E Herruzo Gomez, and JI Benavides Benitez. Optimizing the physical implementation of a reconfigurable cache. In Reconfigurable Computing and FPGAs (ReConFig), 2012 International Conference on, pages 1–6. IEEE, 2012.
George Kalokerinos, Vassilis Papaefstathiou, George Nikiforos, Stamatis Kavadias, Manolis Katevenis, Dionisios Pnevmatikatos, and Xiaojun Yang. FPGA implementation of a configurable cache/scratchpad memory with virtualized user-level RDMA capability. In Systems, Architectures, Modeling, and Simulation, 2009. SAMOS’09. International Symposium on, pages 149–156. IEEE, 2009.
Yen-Jen Chang, Kun-Lin Tsai, and Hsiang-Jen Tsai. Low leakage TCAM for IP lookup using two-side self-gating. IEEE Transactions on Circuits and Systems I: Regular Papers, 60(6):1478–1486, 2013.
S Matsunaga, N Sakimura, R Nebashi, Y Tsuji, A Morioka, T Sugibayashi, S Miura, H Honjo, K Kinoshita, H Sato, et al. Fabrication of a 99%-energy-less nonvolatile multi-functional CAM chip using hierarchical power gating for a massively-parallel full-text-search engine. In VLSI Circuits (VLSIC), 2013 Symposium on, pages C106–C107. IEEE, 2013.
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. 16Kb hybrid TFET/CMOS reconfigurable CAM/SRAM array based on 9T-TFET bitcell. In Solid-State Device Research Conference (ESSDERC), 2016 46th European, pages 356–359. IEEE, 2016.
Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same, author=Proebsting, Robert J and Park, Kee and Chu, Scott Yu-Fan, January 4 2005. US Patent 6,839,256.
Amit Agarwal, Steven Hsu, Sanu Mathew, Mark Anders, Himanshu Kaul, Farhana Sheikh, and Ram Krishnamurthy. A 128× 128b high-speed wide-and match-line content addressable memory in 32nm CMOS. In ESSCIRC (ESSCIRC), 2011 Proceedings of the, pages 83–86. IEEE, 2011.
Anh Tuan Do, Chun Yin, Kiat Seng Yeo, and Tony Tae-Hyoung Kim. Design of a power-efficient CAM using automated background checking scheme for small match line swing. In ESSCIRC (ESSCIRC), 2013 Proceedings of the, pages 209–212. IEEE, 2013.
Chua-Chin Wang, Chia-Hao Hsu, Chi-Chun Huang, and Jun-Han Wu. A self-disabled sensing technique for content-addressable memories. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(1):31–35, 2010.
Mrigank Sharad, Deliang Fan, and Kaushik Roy. Ultra low power associative computing with spin neurons and resistive crossbar memory. In Design Automation Conference (DAC), 2013 50th ACM/EDAC/IEEE, pages 1–6. IEEE, 2013.
Yuanfan Yang, Jimson Mathew, and Dhiraj K Pradhan. Matching in memristor based auto-associative memory with application to pattern recognition. In Signal Processing (ICSP), 2014 12th International Conference on, pages 1463–1468. IEEE, 2014.
Amirali Ghofrani, Abbas Rahimi, Miguel A Lastras-Montaño, Luca Benini, Rajesh K Gupta, and Kwang-Ting Cheng. Associative Memristive Memory for Approximate Computing in GPUs. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 6(2):222–234, 2016.
Mohsen Imani, Abbas Rahimi, and Tajana S Rosing. Resistive configurable associative memory for approximate computing. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, pages 1327–1332. IEEE, 2016.
Mohsen Imani, Pietro Mercati, and Tajana Rosing. ReMAM: low-energy resistive multi-stage associative memory for energy efficient computing. In Quality Electronic Design (ISQED), 2016 17th International Symposium on, pages 101–106. IEEE, 2016.
Mohsen Imani, Shruti Patil, and Tajana Rosing. Approximate computing using multiple-access single-charge associative memory. IEEE Transactions on Emerging Topics in Computing, 2016.
Hang Zhang, Mateja Putic, and John Lach. Low-power gpgpu computation with imprecise hardware. In Proceedings of the 51st Annual Design Automation Conference, pages 1–6. ACM, 2014.
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Gupta, N., Makosiej, A., Amara, A., Vladimirescu, A., Anghel, C. (2021). Content-Addressable Memories. In: TFET Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-55119-3_6
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DOI: https://doi.org/10.1007/978-3-030-55119-3_6
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