Abstract
Cost and power efficiency are an important aspect for applications such as Internet-of-Things (IoT) and Wireless-Sensor Nodes (WSN). In SoCs optimized for these specification, key focus is put on SRAMs and flip-flops as they are the main contributors to area, energy, and leakage. Flip-flops in particular are critical components for synchronous logic and microprocessor-based systems where they are used as pipeline registers, register files, and data-buffers. These systems are often used in applications, which may run on energy scavenging/small batteries requiring low-voltage operation. In IoT applications a small form factor is important as even for a low- to medium-performance microprocessor more than 1000 flip-flops are required; therefore, optimizing area of flip-flops is an important consideration for IoT SoCs.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Costin Anghel, Anju Gupta, Amara Amara, Andrei Vladimirescu, et al. 30-nm tunnel FET with improved performance and reduced ambipolar current. IEEE Transactions on Electron Devices, 58(6):1649–1654, 2011.
Dejan Markovic, Borivoje Nikolic, and Robert Brodersen. Analysis and design of low-energy flip-flops. In Proceedings of the 2001 international symposium on Low power electronics and design, pages 52–55. ACM, 2001.
R Ramanarayanan, N Vijaykrishnan, and MJ Irwin. Characterizing dynamic and leakage power behavior in flip-flops. In ASIC/SOC Conference, 2002. 15th Annual IEEE International, pages 433–437. IEEE, 2002.
SH Rasouli, A Amirabadi, A Seyedi, and Ali Afzali-Kusha. Double edge triggered feedback flip-flop in sub 100nm technology. In Design Automation, 2006. Asia and South Pacific Conference on, pages 6–pp. IEEE, 2006.
Matthew Cotter, Huichu Liu, Suman Datta, and Vijaykrishnan Narayanan. Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications. In Quality electronic design (ISQED), 2013 14th international symposium on, pages 430–437. IEEE, 2013.
Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara, and Costin Anghel. Ultra-low-power compact TFET flip-flop design for high-performance low-voltage applications. In Quality Electronic Design (ISQED), 2016 17th International Symposium on, pages 107–112. IEEE, 2016.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2021 Springer Nature Switzerland AG
About this chapter
Cite this chapter
Gupta, N., Makosiej, A., Amara, A., Vladimirescu, A., Anghel, C. (2021). TFET NDR Flip-Flop. In: TFET Integrated Circuits. Springer, Cham. https://doi.org/10.1007/978-3-030-55119-3_5
Download citation
DOI: https://doi.org/10.1007/978-3-030-55119-3_5
Published:
Publisher Name: Springer, Cham
Print ISBN: 978-3-030-55118-6
Online ISBN: 978-3-030-55119-3
eBook Packages: EngineeringEngineering (R0)