Exploiting Bit-Level Design Techniques in Behavioural Synthesis

Abstract

Most conventional high-level synthesis algorithms and commercial tools handle specification operations in a very conservative way, as they assign operations to one or several consecutive clock cycles, and to one functional unit of equal or larger width. Independently of the parameter to be optimized, area, execution time, or power consumption, more efficient implementations could be derived from handling operations at the bit level. This way, one operation can be decomposed into several smaller ones that may be executed in several inconsecutive cycles and over several functional units. Furthermore, the execution of one operation fragment can begin once its input operands are available, even if the calculus of its predecessors finishes at a later cycle, and also arithmetic properties can be partially applied to specification operations. These design strategies may be either exploited within the high-level synthesis, or applied to optimize behavioural specifications or register-transfer-level implementations.