Abstract
Single-chip multiprocessor(CMP) architecture provides an important research direction for the future microprocessors. A CMP architecture(TCMP) is put forward on the basis of the prior researches on RISC microprocessor. T-CMP integrating two MIPS-based processors is a closely coupled multiprocessor, engaging aggressive thread-level and process-level parallel techniques to improve the performance. This paper presents the key techniques of its implementation, including hardware construction and software design. A functional verification simulator is also developed to simulate the behavior of program executions in the mode of cycle-by-cycle. The results show that the design can improve the computing performance effectively.
This paper is supported by National Natural Science Foundation of China and “863” Fundamental Science Program of China and China Postdoctoral Science Foundation.
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Yao, W., Wang, D., Zheng, W., Guo, S. (2005). Architecture Design of a Single-chip Multiprocessor. In: Zhang, W., Tong, W., Chen, Z., Glowinski, R. (eds) Current Trends in High Performance Computing and Its Applications. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-27912-1_16
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DOI: https://doi.org/10.1007/3-540-27912-1_16
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-25785-1
Online ISBN: 978-3-540-27912-9
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