Summary
Matrix multiplication is one of the most fundamental and computationally intense operation that is used in a variety of scientific and engineering applications. There are many implementations of this normally O(n3) operation. These implementations differ mainly in terms of algorithms or the platforms. In this paper we present our experimentation of using a reconfigurable computing platform for calling such a routine. This routine use our own developed IEEE-754 compliant double precision hardware library elements implemented on our own developed FPGA based reconfigurable platform to provide acceleration.
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Sajish, C., Abhyankar, Y., Ghotgalkar, S., Venkates, K. (2005). Floating Point Matrix Multiplication on a Reconfigurable Computing System. In: Zhang, W., Tong, W., Chen, Z., Glowinski, R. (eds) Current Trends in High Performance Computing and Its Applications. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-27912-1_11
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DOI: https://doi.org/10.1007/3-540-27912-1_11
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-25785-1
Online ISBN: 978-3-540-27912-9
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