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Testing of Synchronizers in Asynchronous FIFO

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Abstract

This paper presents a test method for testing two-D-flip-flop synchronizers in an asynchronous first-in-first-out (FIFO) interface. A faulty synchronizer can have different fault behaviors depending on the input application time, the fault location, the fault mechanism, and the applied clock frequency. The proposed test method can apply the input patterns at different time and generate capture clock signals with different frequency regardless of phase-locked loop (PLL) of the design. To implement the proposed test method, channel delay compensator, delayed scan enable signal generator, launch clock generator, and capture clock generator are designed. In addition, a well-designed calibration method is proposed to calibrate all programmable delay elements used in the test circuits. The proposed test method evolves to several test sections to detect all possible faults of the two-D-flip-flop synchronizers in the asynchronous FIFO interface.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Cincinnati, Cincinnati, OH, 45221, USA

    Hyoung-Kook Kim & Wen-Ben Jone

  2. SynTest Technologies, Inc., 505 South Pastoria Ave., Suite 101, Sunnyvale, CA, 94086, USA

    Laung-Terng Wang

  3. Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shattin, Hong Kong

    Yu-Liang Wu

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  1. Hyoung-Kook Kim
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  2. Laung-Terng Wang
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  3. Yu-Liang Wu
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  4. Wen-Ben Jone
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Correspondence to Hyoung-Kook Kim.

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Responsible Editor: S. Hamdioui

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Kim, HK., Wang, LT., Wu, YL. et al. Testing of Synchronizers in Asynchronous FIFO. J Electron Test 29, 49–72 (2013). https://doi.org/10.1007/s10836-013-5349-0

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