Abstract
Currently, most integrated circuits have higher density of transistors on the small physical area, reduced power consumption and greater performance. An important factor that has contributed for this is the representation of logic functions with a reduced number of transistors. While the generation of a series–parallel network can be straightforward once a minimized Boolean expression is available, this may not be an optimum solution. This paper proposes a graph-based solution for minimizing the number of transistors that compose a network by edges sharing. The algorithm starts from a sum-of-products expression and can achieve non-series-parallel arrangements. The Wheatstone bridge arrangements contribute for the transistor count reduction. Experimental results demonstrate the efficiency of the approach when comparing to traditional factorization algorithms implemented in the SIS software. When applying to the set of four input p-class logic functions, the proposed method presents advantages if compared to the good-factor algorithm.
Similar content being viewed by others
References
Brayton, R. K. (1987). Factoring logic functions. IBM Journal of Research and Development, 31(2), 187–198.
Mintz, A., & Golumbic, M. C. (2005). Factoring Boolean functions using graph partitioning. Discrete Applied Mathematics, 149(1–3), 131–153.
Golumbic, M. C., Mintz, A., & Rotics, U. (2008). An improvement on the complexity of factoring read-once Boolean functions. Discrete Applied Mathematics, 156(10), 1633–1636.
Yoshida, H., Ikeda, M., & Asada, K (2006). Exact minimum logic factoring via quantified Boolean satisfiability. In International conference on electronics, circuits, and systems (pp. 1065–1068). Venice: ICECS.
Dietmeyer, D. L. (1971). Logic design of digital systems. Needham Heights: Allyn and Bacon.
Wu, M., Shu, W., & Chan, S. (1985). A unified theory for MOS circuit design switching network logic. International Journal of Electronics, 58(1), 1–33.
Kohavi, Z. (1970). Switching and finite automata theory. New York: McGraw-Hill.
Zhu, J., & Abd-El-Barr, M. (1993). On the optimization of MOS circuits. IEEE Transactions on Circuits and Systems: Fundamental Theory and Applications, 40(6), 412–422.
Kagaris, D., et al. (2007). A methodology for transistor-efficient supergate design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 15(4), 488–492.
Karnaugh, M. (1953). The map method for the synthesis of combinational circuits. AIEE Transactions, 72(9), 593–599.
Quine, W. V. (1955). A way to simplify truth functions. American Mathematical Monthly, 62, 627–631.
McCluskey, E. J. (1956). Minimization of Boolean functions. Bell Systems Technical Journal, 35, 1417–1444.
Mcgeer, P., et al. (1993). Espresso-signature: A new exact minimizer for logic functions. In Design automation conference (pp. 509–516). Dallas: DAC.
Buch, P., et al. (1997). Logic synthesis for large pass transistor circuits. In ICCAD, proceedings (pp. 663–670). New York: IEEE.
Hsiao, S., Yeh, J., & Chen, D. (2000). High performance multiplexer-based logic synthesis using pass-transistor logic. In ISCAS, Geneva proceedings (pp. 325–328). Piscataway: IEEE.
Shelar, R., & Sapatnekar, S. (2002). An efficient algorithm for low power pass transistor logic synthesis. In ASPDAC, proceedings (pp. 87–92). Shanghai: ASPDAC.
Shelar, R., & Sapatnekar, S. (2001). Recursive bipartitioning of BDDs for performance driven synthesis of pass transistor logic circuits. In ICCAD, proceedings, (pp. 449–452). Portland: ICCAD.
Avci, M., & Yildirim, T. (2003). General design method for complementary pass transistor logic circuits. Electronics Letters, 39(1), 46–48.
Da Rosa Jr., L., Marques, F., Schneider, F., Ribas, R., & Reis, A. (2007). A comparative study of cmos gates with minimum transistor stacks. In 20th ACM symposium on integrated circuits and systems design (pp. 93–98). Monterey: ACM.
Da Rosa Jr., L. S., Schneider, F., Ribas, R. P., & Reis, A. I. (2009). Switch level optimization of digital CMOS gate networks. In 10th IEEE international symposium on quality electronic design (pp. 324–329). Yokohama: ISQED’09.
Prefuse.org. 2011. The prefuse visualization toolkit. Retrieved March 19, 2011 from http://prefuse.org/.
Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Brayton, R., & Sangiovanni-Vincentelli, A. (1992). SIS: A system for sequential circuit synthesis. In Technical Report UCB/ERL M92/41. Berkeley: UC.
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Possani, V.N., de Souza, R.S., Domingues, J.S. et al. Optimizing transistor networks using a graph-based technique. Analog Integr Circ Sig Process 73, 841–850 (2012). https://doi.org/10.1007/s10470-012-9874-z
Received:
Revised:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10470-012-9874-z