Skip to main content
SpringerLink
Log in

Analog to Digital Conversion

  • Chapter
  • First Online:
Low-Power High-Resolution Analog to Digital Converters

Part of the book series: Analog Circuits and Signal Processing ((ACSP))

Abstract

Since the existence of digital signal processing, A/D converters have been playing a very important role to interface analog and digital worlds. They perform the digitalization of analog signals at a fixed time period, which is generally specified by the application. The A/D conversion process involves sampling the applied analog input signal and quantizing it to its digital representation by comparing it to reference voltages before further signal processing in subsequent digital systems. Depending on how these functions are combined, different A/D converter architectures can be implemented with different requirements on each function. To implement power-optimized A/D converter functions, it is important to understand the performance limitations of each function before discussing system issues. In this section, the concept of the basic A/D conversion process and the fundamental limitation to the power dissipation of each key building block are presented.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 54.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. A. Yukawa, An 8-bit high-speed CMOS A/D converter. IEEE J. Solid-State Circuits 20(3), 775–779 (1985)

    Article  Google Scholar 

  2. T. Kumamoto, M. Nakaya, H. Honda, S. Asai, Y. Akasaka, Y. Horiba, An 8-bit high-speed CMOS A/D converter. IEEE J. Solid-State Circuits 21(6), 976–982 (1986)

    Article  Google Scholar 

  3. B. Peetz, B.D. Hamilton, J. Kang, An 8-bit 250 megasample per second analog-to-digital converter: operation without a sample and hold. IEEE J. Solid-State Circuits 21(6), 997–1002 (1986)

    Article  Google Scholar 

  4. Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, H. Ikawa, A 400 MSPS 8 b flash AD conversion LSI. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 27–28, 1987

    Google Scholar 

  5. Y. Gendai, Y. Komatsu, S. Hirase, M. Kawata, An 8b 500MHz ADC. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 172–173, 1991

    Google Scholar 

  6. N. Shiwaku, Y. Tung, T. Hiroshima, K.-S. Tan, T. Kurosawa, K. McDonald, M. Chiang, A rail-to-rail video-band full Nyquist 8-bit A/D converter. Proceedings of IEEE Custom Integrated Circuits Conference, pp. 26.2.1–26.2.4, 1991

    Google Scholar 

  7. K.J. McCall, M.J. Demler, M.W.A. Plante, A 6-bit 125 MHz CMOS A/D converter. Proceedings of IEEE Custom Integrated Circuits Conference, pp. 16.8.1–16.8.4, 1992

    Google Scholar 

  8. I. Mehr, D. Dalton, A 500 Msample/s 6–bit Nyquist rate ADC for disk drive read channel applications. Proceedings of IEEE European Solid-State Circuits Conference, pp. 236–239, 1998

    Google Scholar 

  9. K. Yoon, S. Park, W. Kim, A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 326–327, 1999

    Google Scholar 

  10. B. Yu, W.C. Black Jr., A 900 MS/s 6b interleaved CMOS flash ADC. Proceedings of IEEE Conference on Custom Integrated Circuits, pp. 149–152, 2001

    Google Scholar 

  11. M. Choi, A.A. Abidi, A 6-b 1.3-Gsample/s A/D converter in 0.35-μm CMOS. IEEE J. Solid-State Circuits 36(12), 1847–1858 (2001)

    Article  Google Scholar 

  12. G. Geelen, A 6 b 1.1 GSample/s CMOS A/D converter. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 128–129, 2001

    Google Scholar 

  13. J. Lin, B. Haroun, An embedded 0.8 V/480 μW 6b/22 MHz flash ADC in 0.13 μm digital CMOS process using nonlinear double-interpolation technique. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 244–246, 2002

    Google Scholar 

  14. K. Uyttenhove, M. Steyaert, A 1.8–V, 6–bit, 1.3–GHz CMOS flash ADC in 0.25 μm CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 455–458, 2002

    Google Scholar 

  15. X. Jiang, Z. Wang, M.F. Chang, A 2 GS/s 6 b ADC in 0.18-μm CMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 322–323, 2003

    Google Scholar 

  16. C. Sandner, M. Clara, A. Santner, T. Hartig, F. Kuttner, A 6bit, 1.2GSps low-power flash-ADC in 0.13 μm digital CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 339–342, 2004

    Google Scholar 

  17. C. Paulus, H.-M. Bluthgen, M. Low, E. Sicheneder, N. Bruls, A. Courtois, M. Tiebout, R. Thewes, A 4GS/s 6b flash ADC in 0.13-μm CMOS. IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 420–423, 2004

    Google Scholar 

  18. C.-C. Huang, J.-T. Wu, A Background Comparator Calibration Technique for Flash Analog-to-Digital Converters. IEEE Trans Circuits Syst 52(9), 1732–1740 (2005)

    Article  Google Scholar 

  19. O. Viitala, S. Lindfors, K. Halonen, A 5-bit 1-GS/s Flash-ADC in 0.13-μm CMOS Using Active Interpolation. Proceedings of IEEE European Solid-State Circuits Conference, pp. 412–415, 2006

    Google Scholar 

  20. S. Park, Y. Palaskas, M.P. Flynn, A 4-GS/s 4-bit flash ADC in 0.18-μm CMOS. IEEE J. Solid-State Circuits 42(9), 1865–1872 (2007)

    Article  Google Scholar 

  21. I.-H. Wang, S.-I. Liu, A 1V 5-Bit 5GSample/sec CMOS ADC for UWB receivers. Proceedings of IEEE International Symposium on VLSI Design, Automation and Test, pp. 1–4, 2007

    Google Scholar 

  22. M. Ishikawa, T. Tsukahara, An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H. IEEE J. Solid-State Circuits 24(6), 1485–1491 (1989)

    Article  Google Scholar 

  23. S. Hosotani, T. Miki, A. Maeda, N. Yazawa, An 8bit 20MS/s CMOS A/D converter with 50-mW power consumption. IEEE J. Solid-State Circuits 25(1), 167–172 (1990)

    Article  Google Scholar 

  24. T. Matsuura, H. Kojima, E. Imaizumi, K. Usui, S. Ueda, An 8b 50 MHz 225 mW submicron CMOS ADC using saturation eliminated comparators. Proceedings of IEEE Custom Integrated Circuits Conference, pp 6.4.1–6.4.4, 1990

    Google Scholar 

  25. B. Razavi, B.A. Wooley, A 12b 5MSample/s two-step CMOS A/D converter. IEEE J. Solid-State Circuits 27(12), 1667–1678 (1992)

    Article  Google Scholar 

  26. S.-H. Lee, B.-S. Song, Digital-domain calibration of multistep analog-to-digital converters. IEEE J. Solid-State Circuits 27(12), 1679–1688 (1992)

    Article  Google Scholar 

  27. T. Miki, H. Kouno, T. Kumamoto, Y. Kinoshita, T. Igarashi, K. Okeda, A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter. IEEE J. Solid-State Circuits 29(4), 516–522 (1994)

    Article  Google Scholar 

  28. M. Ito, T. Miki, S. Hosotani, T. Kumamoto, Y. Yamashita, M. Kijima, T. Okuda, K. Okada, A 10 bit 20MS/s 3V Supply CMOS A/D Converter. IEEE J. Solid-State Circuits 29(12), 1531–1531 (1994)

    Article  Google Scholar 

  29. S.-U. Kwak, B.-S. Song, K. Bacrania, A 15 b 5 MSample/s low-spurious CMOS ADC. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 146–147, 1997

    Google Scholar 

  30. H. van der Ploeg, R. Remmers, A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μm CMOS. IEEE J. Solid-State Circuits 34(12), 1803–1811 (1999)

    Article  Google Scholar 

  31. C. Moreland, F. Murden, M. Elliott, J. Young, M. Hensley, R. Stop, A 14-bit 100-MSample/s subranging ADC. IEEE J. Solid-State Circuits 35(7), 1791–1798 (2000)

    Article  Google Scholar 

  32. P. Hui, M. Segami, M. Choi, C. Ling, A.A. Abidi, A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μm CMOS with over 80-dB SFDR. IEEE J. Solid-State Circuits 35(12), 1769–1780 (2000)

    Article  Google Scholar 

  33. M.-J. Choe, B.-S. Song, K. Bacrania, A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming. IEEE J. Solid-State Circuits 35(6), 1781–1790 (2000)

    Article  Google Scholar 

  34. H. van der Ploeg, G. Hoogzaad, H.A.H. Termeer, M. Vertregt, R.L.J. Roovers, A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2 with mixed-signal chopping and calibration. IEEE J. Solid-State Circuits 36(12), 1859–1867 (2001)

    Article  Google Scholar 

  35. M. Clara, A. Wiesbauer, F. Kuttner, A 1.8 V Fully Embedded 10 b 160 MS/s Two-Step ADC in 0.18 μm CMOS. Proceedings of IEEE Custom Integrated Circuit Conference, pp. 437–440, 2002

    Google Scholar 

  36. T.-C. Lin, J.-C. Wu, A two-step A/D converter in digital CMOS processes. Proceedings of IEEE Asia-Pacific Conference on ASIC, pp. 177–180, 2002

    Google Scholar 

  37. A. Zjajo, H. van der Ploeg, M. Vertregt, A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μm CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 241–244, 2003

    Google Scholar 

  38. H. van der Ploeg, M. Vertregt, M. Lammers, A 15-bit 30 MS/s 145 mW three-step ADC for imaging applications. Proceedings of IEEE European Solid-State Circuits Conference, pp. 161–164, 2005

    Google Scholar 

  39. N. Ning, F. Long, S.-Y. Wu, Y. Liu, G.-Q. Liu, Q. Yu, M.-H. Yang, An 8-Bit 250MSPS modified two-step ADC. Proceedings of IEEE International Conference on Communications, Circuits and Systems, pp. 2197–2200, 2006

    Google Scholar 

  40. T. Sekino, M. Takeda, K. Koma, A Monolithic 8b Two-Step Parallel ADC without DAC and Subtractor Circuits. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 46–47, 1982

    Google Scholar 

  41. A.G.F. Dingwall, V. Zazzu, An 8-MHz CMOS subranging 8-bit A/D converter. IEEE J. Solid-State Circuits 20(6), 1138–1143 (1985)

    Article  Google Scholar 

  42. J. Fernandes, S.R. Lewis, A.M. Mallinson, G.A. Miller, A 14-bit 10-μs subranging A/D converter with S/H. IEEE J. Solid-State Circuits 23(6), 1309–1315 (1988)

    Article  Google Scholar 

  43. M. Ishikawa, T. Tsukahara, An 8-bit 50-MHz CMOS subranging A/D converter with pipelined wide-band S/H. IEEE J. Solid-State Circuits 24(6), 1485–1491 (1989)

    Article  Google Scholar 

  44. R. Petschacher, B. Zojer, B. Astegher, H. Jessner, A. Lechner, A 10-b 75-MSPS subranging A/D converter with integrated sample and hold. IEEE J. Solid-State Circuits 25(6), 1339–1346 (1990)

    Article  Google Scholar 

  45. G. Sou, G.-N. Lu, G. Klisnick, M. Redon, A 10-bit 20-Msample/s Sub-Ranging ADC for Low-Power and Low-Voltage Applications. Proceedings of IEEE European Solid-State Circuits Conference, pp. 424–427, 1998

    Google Scholar 

  46. A. Wiesbauer, M. Clara, M. Harteneck, T. Potscher, C. Fleischhacker, G. Koder, C. Sandner, a fully integrated analog front-end macro for cable modem applications in 0.18-μm CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 245–248, 2001

    Google Scholar 

  47. R.C. Taft, M.R. Tursi, A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V. IEEE J. Solid-State Circuits 36(3), 331–338 (2001)

    Article  Google Scholar 

  48. J. Mulder, C.M. Ward, C.-H. Lin, D. Kruse, J.R. Westra, M. Lughtart, E. Arslan, R.J. van de Plassche, K. Bult, F.M.L. van der Goes, A 21-mW 8-b 125-MSample/s ADC in 0.09-mm2 0.13-μm CMOS. IEEE J. Solid-State Circuits 39(5), 2116–2125 (2004)

    Article  Google Scholar 

  49. P.M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe, J. Vital, A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 568–569, 2006

    Google Scholar 

  50. Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90 nm digital CMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 216–217, 2006

    Google Scholar 

  51. J. Huber, R.J. Chandler, A.A. Abidi, A 10b 160MS/s 84mW 1V subranging ADC in 90nm CMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 454–455, 2007

    Google Scholar 

  52. C. Cheng, Y. Jiren, A 10-bit 500-MS/s 124-mW subranging folding ADC in 0.13 μm CMOS. Proceedings of IEEE International Symposium on Circuits and Systems, pp. 1709–1712, 2007

    Google Scholar 

  53. Y. Shimizu, S. Murayama, K. Kudoh, H. Yatsuda, A Split-Load Interpolation-amplifier-array 300MS/s 8b subranging ADC in 90 nm CMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 552–553, 2008

    Google Scholar 

  54. S.H. Lewis, P.R. Gray, A pipelined 5-Msample/s 9-bit analog-to-digital converter. IEEE J. Solid-State Circuits 22(4), 954–961 (1987)

    Article  Google Scholar 

  55. S. Sutarja, P. Gray, A pipelined 13-bit, 250-ks/s, 5-V analog-to-digital converter. IEEE J. Solid-State Circuits 23(6), 1316–1323 (1988)

    Article  Google Scholar 

  56. B.-S. Song, M.F. Tompsett, K.R. Lakshmikumar, A 12 bit 1 MHz capacitor error averaging pipelined A/D. IEEE J. Solid-State Circuits 23(10), 1324–1333 (1988)

    Article  Google Scholar 

  57. Y.-M. Lin, B. Kim, P.R. Gray, A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3-μm CMOS. IEEE J. Solid-State Circuits 26(5), 628–635 (1991)

    Article  Google Scholar 

  58. T. Matsuura, M. Hotta, K. Usui, E. Imaizumi, S. Ueda, A 95 mW, 10b 15 MHz low-power CMOS ADC using analog double-sampled pipelining scheme. Proceedings of IEEE Symposium on VLSI Circuits, pp. 98–99, 1992

    Google Scholar 

  59. S.H. Lewis, H.S. Fetterman, G.F. Gross, R. Ramachandran, T.R. Viswanathan, A 10-b 20-Msample/s analog-to-digital converter. IEEE J. Solid-State Circuits 27(3), 351–358 (1992)

    Article  Google Scholar 

  60. C. Mangelsdorf, S.-H. Lee, M. Martin, H. Malik, T. Fukuda, H. Matsumoto, Design for testability in digitally-corrected ADCs. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 70–71, 1993

    Google Scholar 

  61. C. Mangelsdorf, H. Malik, S.-H. Lee, S Hisano, M. Martin, A two residue architecture for mulitstage ADCs. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 64–65, 1993

    Google Scholar 

  62. K. Kusumoto, A. Matsuzawa, K. Murata, A 10 b 20MHz 30 mW pipelined interpolating CMOS ADC. IEEE J. Solid-State Circuits 28(12), 1200–1206 (1993)

    Article  Google Scholar 

  63. A.N. Karanicolas, H.-S. Lee, K.L. Bacrania, A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. IEEE J. Solid-State Circuits 28(12), 1207–1215 (1993)

    Article  Google Scholar 

  64. W.T. Colleran, A.A. Abidi, A 10-b, 75 Ms/s two stage pipelined bipolar A/D converter. IEEE J. Solid-State Circuits 28(12), 1187–1199 (1994)

    Article  Google Scholar 

  65. D.A. Mercer, A 14-b, 2.5 MSPS pipelined ADC with on-chip EPROM. IEEE J. Solid-State Circuits 31(1), 70–76 (1996)

    Article  Google Scholar 

  66. I. Opris, L. Lewicki, B. Wong, A single-ended 12-bit 20 MSample/s self-calibrating pipeline A/D converter. IEEE J. Solid-State Circuits 33(11), 1898–1903 (1998)

    Article  Google Scholar 

  67. A.M. Abo, P.R. Gray, A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. IEEE J. Solid-State Circuits 34(5), 599–606 (1999)

    Article  Google Scholar 

  68. H.-S. Chen, K. Bacrania, B.-S. Song, A 14b 20MSample/s CMOS pipelined ADC. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 46–47, 2000

    Google Scholar 

  69. I. Mehr, L. Singer, A 55-mW, 10-bit, 40-Msample/s Nyquist-rate CMOS ADC. IEEE J. Solid-State Circuits 35(3), 70–76 (2000)

    Article  Google Scholar 

  70. Y. Chiu, Inherently linear capacitor error-avaraging techniques for pipelined A/D conversion. IEEE Trans Circuits Syst–II 47, 229–232 (2000)

    Article  Google Scholar 

  71. B.W. Lee, G.H. Cho, A CMOS 10 bit 37MS/s pipelined A/D converter with code regeneration and averaging. Proceedings of IEEE European Solid-State Circuits Conference, pp. 314–317, 2000

    Google Scholar 

  72. J. Goes, J.C. Vital, L. Alves, N. Ferreira, P. Ventura, E. Bach, J.E. Franca, R. Koch, A low-power 14-b 5 MS/s CMOS pipeline ADC with background analog self-calibration. Proceedings of IEEE European Solid-State Circuits Conference, pp. 172–175, 2000

    Google Scholar 

  73. A. Loloee, A. Zanchi, J. Huawen, S. Shehata, E. Bartolome, A 12b 80MSps pipelined ADC core with 190 mW consumption from 3 V in 0.18 μm digital CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 467–470, 2002

    Google Scholar 

  74. B.-M. Min, P. Kim, F.W. Bowman, D.M. Boisvert, A.J. Aude, A 69-mW 10-bit 80-MSample/s pipelined CMOS ADC. IEEE J. Solid-State Circuits 38(12), 1187–1199 (2003)

    Google Scholar 

  75. T.N. Andersen, A. Briskemyr, F. Telstø, J. Bjørnsen, T. E. Bonnerud, B. Hernes, Ø. Moldsvor, A 97 mW 100 MS/s 12b pipeline ADC implemented in 0.18 μm digital CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 247–250, 2004

    Google Scholar 

  76. J. Li, U.-K. Moon, A 1.8-V 67-mW 10-bit 100-MS/s pipelined ADC using time-shifted CDS technique. IEEE J. Solid-State Circuits 39(9), 1468–1476 (2004)

    Article  Google Scholar 

  77. X. Wang, P.J. Hurst, S.H. Lewis, A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration. IEEE J. Solid-State Circuits 39(11), 1799–1808 (2004)

    Article  Google Scholar 

  78. D. Kurose, T. Ito, T. Ueno, T. Yamaji, T. Itakura, 55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. Proceedings of IEEE European Solid-State Circuits Conference, pp. 527–530, 2005

    Google Scholar 

  79. C.T. Peach, A. Ravi, R. Bishop, K. Soumyanath, D.J. Allstot, A 9-b 400 Msample/s pipelined analog-to-digital converter in 90 nm CMOS. Proceedings of IEEE European Solid-State Circuits Conference, pp. 535–538, 2005

    Google Scholar 

  80. A.M.A. Ali, C. Dillon, R. Sneed, A.S. Morgan, S. Bardsley, J. Kornblum, L. Wu, A 14-bit 125 MS/s IF/RF sampling pipelined ADC with 100 dB SFDR and 50 fs jitter. IEEE J. Solid-State Circuits 41(8), 1846–1855 (2006)

    Article  Google Scholar 

  81. M. Daito, H. Matsui, M. Ueda, K. Iizuka, A 14-bit 20-MS/s pipelined ADC with digital distortion calibration. IEEE J. Solid-State Circuits 41(11), 2417–2423 (2006)

    Article  Google Scholar 

  82. T. Ito, D. Kurose, T. Ueno, T. Yamaji, T. Itakura, 55-mW 1.2-V 12-bit 100-MSPS pipeline ADCs for wireless receivers. Proceedings of IEEE European Solid-State Circuits Conference, pp. 540–543, 2006

    Google Scholar 

  83. J. Treichler, Q. Huang, T. Burger, A 10-bit ENOB 50-MS/s pipeline ADC in 130-nm CMOS at 1.2 V supply. Proceedings of IEEE European Solid-State Circuits Conference, pp. 552–555, 2006

    Google Scholar 

  84. I. Ahmed, D.A. Johns, An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage. Proceedings of IEEE European Solid-State Circuits Conference, pp. 147–150, 2007

    Google Scholar 

  85. S.-C. Lee, Y.-D. Jeon, J.-K. Kwon, J. Kim, A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS pipeline ADC for flat panel display applications. IEEE J. Solid-State Circuits 42(12), 2688–2695 (2007)

    Article  Google Scholar 

  86. J. Li, R. Leboeuf, M. Courcy, G. Manganaro, A 1.8V 10b 210MS/s CMOS pipelined ADC featuring 86 dB SFDR without calibration. Proceedings of IEEE Custom Integrated Circuits Conference, pp. 317–320, 2007

    Google Scholar 

  87. M. Boulemnakher, E. Andre, J. Roux, F. Paillardet, A 1.2V 4.5 mW 10 b 100 MS/s pipeline ADC in a 65nm CMOS. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 250–251, 2008

    Google Scholar 

  88. Y.-S. Shu, B.-S. Song, A 15-bit linear 20-MS/s pipelined ADC digitally calibrated with signal-dependent dithering. IEEE J. Solid-State Circuits 43(2), 342–350 (2008)

    Article  Google Scholar 

  89. J. Shen, P.R. Kinget, A 0.5-V 8-bit 10-Ms/s pipelined ADC in 90-nm CMOS. IEEE J. Solid-State Circuits 43(4), 1799–1808 (2008)

    Article  Google Scholar 

  90. W.C. Black Jr., D.A. Hodges, Time interleaved converter arrays. IEEE J. Solid-State Circuits 15(6), 1022–1029 (1980)

    Article  Google Scholar 

  91. C.S.G. Conroy, D.W. Cline, P.R. Gray, A high-speed parallel pipelined ADC technique in CMOS. Proceedings of IEEE Symposium on VLSI Circuits, pp. 96–97, 1992

    Google Scholar 

  92. M. Yotsuyanagi, T. Etoh, K. Hirata, A 10 b 50 MHz pipelined CMOS A/D converter with S/H. IEEE J. Solid-State Circuits 28, 292–300 (1993)

    Article  Google Scholar 

  93. K. Nagaraj, H. Fetterman, J. Anidjar, S. Lewis, R. Renninger, An 8-b 50-Msamples/s pipelined A/D converter with an area and power efficient architecture. Proceedings of IEEE Custom Integrated Circuits Conference, pp. 423–426, 1996

    Google Scholar 

  94. W. Bright, 8 b 75 M Sample/s 70 mW parallel pipelined ADC incorporating double sampling. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 146–147, 1998

    Google Scholar 

  95. K. Dyer, D. Fu, S. Lewis, P. Hurst, Analog background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid-State Circuits 33(12), 1912–1919 (1998)

    Article  Google Scholar 

  96. D. Fu, K.C. Dyer, S.H. Lewis, P.J. Hurst, A digital background calibration technique for time-interleaved analog-to-digital converters. IEEE J. Solid-State Circuits 33(12), 1904–1911 (1998)

    Article  Google Scholar 

  97. L. Sumanen, M. Waltari, K.A.I. Halonen, A 10-bit 200-MS/s CMOS parallel pipeline A/D converter. Proceedings of IEEE European Solid-State Circuits Conference, pp. 439–442, 2000

    Google Scholar 

  98. S.M. Jamal, D. Fu, N.C.-J. Chang, P.J. Hurst, S.H. Lewis, A 10-b 120-MSample/s time-interleaved analog-to-digital converter with digital background calibration. IEEE J. Solid-State Circuits 37(12), 1618–1627 (2002)

    Article  Google Scholar 

  99. J. Talebzadeh, M.R. Hasanzadeh, M. Yavari, O. Shoaei, A 10-bit 150-MS/s parallel pipeline A/D converter in 0.6-μm CMOS. Proceedings of IEEE International Symposium on Circuits and Systems, pp. 133–136, 2002

    Google Scholar 

  100. D. Subiela, S. Engels, L. Dugoujon, R. Esteve-Bosch, B. Mota, L. Musa, A. Jimenez-de-Parga, A low-power 16-channel AD converter and digital processor ASIC. Proceedings of IEEE European Solid-State Circuits Conference, pp. 259–262, 2002

    Google Scholar 

  101. D. Miyazaki, M. Furuta, S. Kawahito, A 75mW 10bit 120MSample/s parallel pipeline ADC. Proceedings of IEEE European Solid-State Circuits Conference, pp. 719–722, 2003

    Google Scholar 

  102. B. Xia, A. Valdes-Garcia, E. Sanchez-Sinencio, A configurable time-interleaved pipeline ADC for multi-standard wireless receivers. Proceedings of IEEE European Solid-State Circuits Conference, pp. 259–262, 2004

    Google Scholar 

  103. S.-C. Lee, G.-H. Kim, J.-K. Kwon, J. Kim, S.-H. Lee, Offset and dynamic gain-mismatch reduction techniques for 10 b 200 Ms/s parallel pipeline ADCs. Proceedings of IEEE European Solid-State Circuits Conference, pp. 531–534, 2005

    Google Scholar 

  104. S. Limotyrakis, S.D. Kulchycki, D.K. Su, B.A. Wooley, A 150-MS/s 8-b 71-mW CMOS time-interleaved ADC. IEEE J. Solid-State Circuits 40(5), 1057–1067 (2005)

    Article  Google Scholar 

  105. C.-C. Hsu, F.-C. Huang, C.-Y. Shih, C.-C. Huang, Y.-H. Lin, C.-C. Lee, B. Razavi, An 11b 800 MS/s time-interleaved ADC with digital background calibration. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 464–465, 2007

    Google Scholar 

  106. Z.-M. Lee, C.-Y. Wang, J.-T. Wu, A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration. IEEE J. Solid-State Circuits 42(10), 2149–2160 (2007)

    Article  Google Scholar 

  107. R.H. Walden, Analog-to-digital converter survey and analysis. IEEE J. Sel. Areas Commun. 17(4), 539–550 (1999)

    Article  Google Scholar 

  108. K. Kattmann, J. Barrow, A technique for reducing differential nonlinearity errors in flash A/D converters. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 170–171, 1991

    Google Scholar 

  109. K. Bult, A. Buchwald, An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1 mm2. IEEE J. Solid-State Circuits 32(4), 1887–1895 (1997)

    Article  Google Scholar 

  110. H. Kimura, A. Matsuzawa, T. Nakamura, S. Sewada, A 10-b 300-MHz interpolated-parallel A/D converter. IEEE J. Solid-State Circuits 28(5), 438–446 (1993)

    Article  Google Scholar 

  111. B. Ginetti, P. Jespers, A 1.5 MS/s 8-bit pipelined RSD A/D converter. Proceedings of IEEE European Solid-State Circuits Conference, pp. 137–140, 1990

    Google Scholar 

  112. B. Ginetti, P.G.A. Jespers, A. Vandemeulebroecks, A CMOS 13-b cyclic RSD A/D converter. IEEE J. Solid-State Circuits 27(8), 957–965 (1992)

    Article  Google Scholar 

  113. E.G. Soenen, R.L. Geiger, An architecture and an algorithm for fully digital correction of monolithic pipelined ADC’s. IEEE Trans Circuits Syst–II 42, 143–153 (1995)

    Article  Google Scholar 

  114. S.-H. Lee, B.-S. Song, Digital-domain calibration for multistep analog-to-digital converters. IEEE J. Solid-State Circuits 27(5), 1679–1688 (1992)

    Article  Google Scholar 

  115. P.W. Li, M.J. Chin, P.R. Gray, R. Castello, A ratio-independent algorithmic analog-to-digital conversion technique. IEEE J. Solid-State Circuits 19(8), 828–836 (1984)

    Article  Google Scholar 

  116. T. Matsuura, T. Nara, T. Komatsu, E. Imaizumi, T. Matsutsuru, R. Horita, H. Katsu, S. Suzumura, K. Sato, A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. IEEE J. Solid-State Circuits 33(4), 1840–1850 (1998)

    Article  Google Scholar 

  117. K.Y. Kim, N. Kusayanagi, A.A. Abidi, A 10-b, 100-MS/s CMOS A/D converter. IEEE J. Solid-State Circuits 32(8), 302–311 (1997)

    Google Scholar 

  118. J.M. Rabaey, A. Chandrakasan, B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd edn. (Prentice Hall, New Jersey, 2003)

    Google Scholar 

  119. A.A. Abidi, High-frequency noise measurements on FETs with small dimensions. IEEE Trans. Electron Devices 33(11), 1801–1805 (1986)

    Article  Google Scholar 

  120. C. Enz, Y. Cheng, MOS transistor modeling for RF IC design. IEEE J. Solid-State Circuits 35(2), 186–201 (2000)

    Article  Google Scholar 

  121. M. Pelgrom, A. Duinmaijer, A. Welbers, Matching properties of MOS transistors. IEEE J. Solid-State Circuits 24(5), 1433–1439 (1989)

    Article  Google Scholar 

  122. K. Bult, G. Geelen, A fast-settling CMOS Op Amp for SC circuits with 90-dB DC gain. IEEE J. Solid-State Circuits 25(6), 1379–1384 (1990)

    Article  Google Scholar 

  123. G. Nicollini, P. Confalonieri, D. Senderowicz, A fully differential sample-and-hold circuit for high-speed applications. IEEE J. Solid-State Circuits 24(5), 1461–1465 (1989)

    Article  Google Scholar 

  124. K. Gulati, H.-S. Lee, A high-swing CMOS telescopic operational amplifier. IEEE J. Solid-State Circuits 33(12), 2010–2019 (1998)

    Article  Google Scholar 

  125. T.C. Choi, R.T. Kaneshiro, W. Brodersen, P.R. Gray, W.B. Jett, M. Wilcox, High-frequency CMOS switched-capacitor filters for communications application. IEEE J. Solid-State Circuits 18, 652–664 (1983)

    Article  Google Scholar 

  126. R. Harjani, R. Heineke, F. Wang, An integrated low-voltage class AB CMOS OTA. IEEE J. Solid-State Circuits 34(2), 134–142 (1999)

    Article  Google Scholar 

  127. R. Hogervorst, J.H. Huijsing, Design of Low-Voltage Low-Power Operational Amplifier Cells (Kluwer, Dordrecht, 1999)

    Google Scholar 

  128. B.K. Ahuja, An improved frequency compensation technique for CMOS operational amplifiers. IEEE J. Solid-State Circuits 18(6), 629–633 (1983)

    Article  MathSciNet  Google Scholar 

  129. R. Ockey, M. Syrzycki, Optimization of a latched comparator for high-speed analog-to-digital converters. IEEE Canadian Conf Elect Comput Eng 1, 403–408 (1999)

    Google Scholar 

  130. P.M. Figueiredo, J.C. Vital, Low kickback noise techniques for CMOS latched comparators. IEEE Int Symp Circuits Syst 1, 537–540 (2004)

    Google Scholar 

  131. F. Murden, R. Gosser, 12b 50 M Sample/s two-stage A/D converter. IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 278–279, 1995

    Google Scholar 

  132. J. Robert, G.C. Temes, V. Valencic, R. Dessoulavy, D. Philippe, A 16-bit low-voltage CMOS A/D converter. IEEE J. Solid-State Circuits 22(2), 157–263 (1987)

    Article  Google Scholar 

  133. T.B. Cho, P.R. Gray, A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. IEEE J. Solid-State Circuits 30(3), 166–172 (1995)

    Article  Google Scholar 

  134. L. Sumanen, M. Waltari, K. Halonen, A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters. Proceedings of the IEEE International Conference on Circuits and Systems, pp. 32–35, 2000

    Google Scholar 

  135. T. Kobayashi, K. Nogami, T. Shirotori, Y. Fujimoto, A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture. IEEE J. Solid-State Circuits 28(4), 523–527 (1993)

    Article  Google Scholar 

  136. B. Nauta, A.G.W. Venes, A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter. IEEE J. Solid-State Circuits 30(12), 1302–1308 (1995)

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Delft University of Technology, Delft, The Netherlands

    Amir Zjajo

  2. Eindhoven University of Technology, and NXP Semiconductors, Eindhoven, The Netherlands

    José Pineda de Gyvez

Authors
  1. Amir Zjajo
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. José Pineda de Gyvez
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Amir Zjajo .

Rights and permissions

Reprints and permissions

Copyright information

© 2011 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Zjajo, A., de Gyvez, J.P. (2011). Analog to Digital Conversion. In: Low-Power High-Resolution Analog to Digital Converters. Analog Circuits and Signal Processing. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9725-5_2

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-9725-5_2

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-9724-8

  • Online ISBN: 978-90-481-9725-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation