Skip to main content
SpringerLink
Log in

NAND DDR interface

  • Chapter
  • First Online:
Inside NAND Flash Memories

Abstract

Nowadays NAND Flash memory is pervading every type of electronic application. The availability of cheap storage memory, in combination with high densities, makes up the choice in favor of NAND Flash on board of applications traditionally linked to other types of memories (such as EEPROM and NOR) or technologies (such as Hard Disk Drives). Mobile devices, PDA, PC, camcorders, set top boxes, servers, routers, enterprise storage and many more new applications requiring a storage media will have to deal with NAND Flash in the coming years. The memories environment has changed since year 2001 when growth rate for NAND surpassed the ‘Moore law’ observed for processor growth and predicting a double density every eighteen months. By then, NAND devices with double density have been introduced every year. In addition, MLC devices with 2 bit/cell entered volume production.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 189.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 249.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 249.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Similar content being viewed by others

References

  1. www.onfi.org

  2. http://www.intel.com/standards/nvmhci/index.htm

  3. https://www.denali.com/en/events/webcasts/2008/togglenand/

  4. G. Campardo, R. Micheloni, D. Novosel, VLSI-Design of Non-Volatile Memories, Springer-verlag, Heidelberg, 2005.

    Google Scholar 

  5. S. Dabral T., Maloney Basic ESD and I/O Design, Wiley-Interscience, New York,1998

    Google Scholar 

  6. B. Jacob, Spencer W. Ng, David T. Wang, Memory Systems: Cache, DRAM, Disk, Morgan Kaufman, CA,2007

    Google Scholar 

  7. S.H. HallGarrett, W. HallJames, A. McCall, High-Speed Digital System Design-A Handbook of Interconnect Theory and Design Practices, Wiley-Interscience, New York,2000

    Google Scholar 

  8. JEDEC JESD79-2C

    Google Scholar 

  9. T. Wada, M.E. Kenji Mami, Simple Noise Model and Low-Noise Data-Output Buffer for Ultrahigh-speed Memories, IEEE Journal of Solid-State Circuits, Vol. 25, No. 6, Dec. 1990.

    Google Scholar 

  10. H.B. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Boston, MA, 1990.

    Google Scholar 

  11. M. Annaratone, Digital CMOS Crcuit Design, Kluwer, Boston, MA, 1986.

    Google Scholar 

  12. www.esda.org

  13. Shyh-Jye Jou et al, Low Switching Noise and Load-Adaptive Output Buffer Design Techniques, IEEE Journal of Solid-State Circuits, Vol. 36, No. 8, pp. 1239–1249, 2001.

    Article  MathSciNet  Google Scholar 

  14. P. Heydari, M. Pedram, Ground Bounce in digital VLS circuits, IEEE Transactions on VLSI Systems, Vol. 11, Issue 2, pp. 180–193, April 2003.

    Article  Google Scholar 

  15. R. Senthinathan, J.L. Prince, “Simultaneous Switching Ground Noise Calculation for Packaged CMOS Devices,” IEEE Journal of Solid-State Circuits, Vol. 26, pp. 1724–1728, Nov. 1991.

    Article  Google Scholar 

  16. R. Senthinathan, J.L. Prince, Simultaneous Switching Noise of CMOS Devices and Systems, Kluwer, Boston, MA, 1994.

    Google Scholar 

  17. E. Chioffi, F. Maloberti, and others, “High-Speed, Low-Switching Noise CMOS Memory Data Output Buffer,” IEEE Journal of Solid-State Circuits, Vol. 29, No. 11, pp. 1359–1365, November 1994.

    Article  Google Scholar 

  18. T. Gabara, W. Fischer, and others, “Forming Damped LRC Parasitic Circuits in Simultaneously Switched CMOS Output Buffers,” IEEE Journal of Solid-State Circuits, Vol. 32, p. 407, 1997.

    Article  Google Scholar 

  19. K. Asahina, S. Kato, and S. Kayano, “Output Buffer with On-Chip Compensation Circuit,” Proceedings of 1993 Custom Integrated Circuit Conference, pp. 29.1.1–29.1.4, May 1993.

    Google Scholar 

  20. T. Sekiguchi, M. Horiguchi et al, “Low-Noise, High-Speed Data Transmission Using a Ringing-Canceling Output Buffer,” IEEE Journal of Solid-State Circuits, Vol. 30, No. 12, pp. 1569–1574, Dec. 1995.

    Article  Google Scholar 

  21. C.H. Lim, W.R. Daasch, “Output Buffer with Self-Adjusting Slew Rate and On-Chip Compensation IC/Package Design Integration,” Proceedings of 1998 IEEE Symposium on IC/Package Design Integration, Issue 2–3, Page(s): 51–55, Feb. 1998.

    Google Scholar 

  22. M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John Edmondson, and John Poulton, CMOS High-Speed I/Os - Present and Future, 2003 IEEE International Conference on Computer Design (ICCD03), Oct. 2003

    Google Scholar 

  23. H. Hikeda, A 3D Packaging with 4Gb Chip-Stacked DRAM and 3Gbps High-Speed Logic 3D-SIC,2007.

    Google Scholar 

  24. J. Poulton, Signaling in High-Performance Memory Systems 1999 ISSCC.

    Google Scholar 

  25. T.J. Gabara, S.C. Knauer, Digitally adjustable resistors in CMOS for High-performance applications, IEEE JSSC, 27, p 1176, 1992.

    Google Scholar 

  26. A. Chandrakasan and R. Brodersen, Eds., Low Power CMOS Design, Kluwer, Boston, MA, 1995.

    Google Scholar 

  27. B. Deutschmann, T. Ostermann, CMOS Output Driver With Reduced Ground Bounce and Electromagnetic emission, Solid-State Circuits Conference, 2003. ESSCIRC 03.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Forward Insights, North York, Canada

    Andrea Silvagni

Authors
  1. Andrea Silvagni
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Andrea Silvagni .

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer Science+Business Media B.V.

About this chapter

Cite this chapter

Silvagni, A. (2010). NAND DDR interface. In: Inside NAND Flash Memories. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9431-5_7

Download citation

  • DOI: https://doi.org/10.1007/978-90-481-9431-5_7

  • Published:

  • Publisher Name: Springer, Dordrecht

  • Print ISBN: 978-90-481-9430-8

  • Online ISBN: 978-90-481-9431-5

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation