Abstract
The core of a contemporary CPLD device is a PAL-based logic block which consists of a programmable AND matrix and a fixed OR matrix. A new technology mapping method for PAL-based devices based on the analysis of graph of outputs is described. The presented approach uses original method for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with common output part. The essence of the method is the process of searching for appropriate multi-output implicants that can be shared by several functions. A new method for the description of cascaded feedback connections is presented. The experimental results show that the proposed algorithm leads to significant reduction of chip area used by resulting circuits.
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Kania, D. (2011). 6 Efficient Technology Mapping Method for PAL-Based Devices. In: Adamski, M., Barkalov, A., Węgrzyn, M. (eds) Design of Digital Systems and Devices. Lecture Notes in Electrical Engineering, vol 79. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17545-9_6
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DOI: https://doi.org/10.1007/978-3-642-17545-9_6
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