Abstract
Parallel-prefix adders (also known as carry tree adders) are known to have the best Performance in VLSI designs. The Design of the three types of carry-tree adders namely Kogge-Stone, sparse Kogge-Stone, and spanning carry look ahead adder is done and compares them to the simple Ripple Carry Adder (RCA). These designs of varied bit-widths were implemented on a Xilinx Spartan 3E FPGA and power measurements were made with LIBRO. Due to the presence of a fast carry-chain, the RCA designs exhibit better delay performance up to 128 bits. The carry-tree adders are expected to have a speed advantage over the RCA as bit widths approach 256. An Efficient FFT is designed by implementing the adder which consumes low power is replaced in the adder module of FFT.
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References
Westte NHE, Harris D (2011) CMOS VLSI Design, Pearson-Addison-Wesley, 4th edn
Brent RP, Kung, HT (1982) A regular layout for parallel adders. IEEE Trans Comput C-31:260–264
Harris D (2003) A taxonomy of parallel prefix networks. In: Proceeding 37th Asilomar conference signals systems and computers, pp 2213–2217
Kogge PM, Stone HS (1973) A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans Comput C-22(8):786–793
Ndai P, Lu S, Somesekhar D, Roy K (2007) Fine grained redundancy in adders. In: International symposium on quality electronic design pp 317–321
Lynch T, Swartzlander EE (1992) A spanning tree carry look ahead adder. IEEE Trans Comput 41(8):931–939
Gizopoulos D, Psarakis M, Paschalis A, Zorian Y (2003) Easily testable cellular carry look ahead adders. J Elect Test Theory Appl 19:285–293
Xing S, Yu WWH (1998) FPGA adders: performance evaluation and optimal design. IEEE Des Test Comput 15(1):24–29
Becvar M, Stukjunger P (2005) Fixed point arithmetic in FPGA. ActaPolytechnicia 45(2):67–72
Virtoroulis K, Al-Khalili SJ. Perfromance of parallel prefix adders implemented with FPGA technology
Ghosh S, Patrick N, Kaushik R (2008) A novel low overhead fault tolerant Kogge‐stone adder using adaptive clocking
Rabaey J (1996) Digital integrated circuits: a design perspective. Prentice Hall, India
Brent RP, Kung HT (1982) A regular layout for parallel adders. IEEE Tr Comp C-31(3):260–264
Gurkaynak FK et al (2000) Higher radix KS parallel prefix adder architectures. ISCAS, May
Han T, Carlson DA (1987) Fast area-efficient VLSI adders. In: 8th Symposium on Computer Arithmetic
Knowles S (1999) A family of adders. In: Symposium on Computer Arithmetic
Kogge P, Stone H (1973) A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Trans Comp C-22(8):786–793
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SreenathKashyap, S. (2013). High Through-Put VLSI Architecture for FFT Computation. In: Das, V. (eds) Proceedings of the Third International Conference on Trends in Information, Telecommunication and Computing. Lecture Notes in Electrical Engineering, vol 150. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-3363-7_1
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DOI: https://doi.org/10.1007/978-1-4614-3363-7_1
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