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Variability in Nanometer Technologies and Impact on SRAM

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Nanometer Variation-Tolerant SRAM

Abstract

In recent technologies, there is a high demand to integrate large embedded memories in microprocessors and SoCs. In addition, SRAM bitcell area scaling continues to follow an aggressive 50 % reduction each technology node. Technology scaling and the reduction in device sizes increase variations, which have a strong impact on SRAM operation. In this chapter, we review different types of variations that affect SRAM. We start by presenting the SRAM scaling trends in Sect. 2.1. Next, in Sects. 2.2–2.5, we briefly review sources of variability in nanometer CMOS technology including device, interconnect, and environmental variations. The impact of variations on SRAM operation is presented in Sect. 2.6. Due to the similarities between SRAM and logic circuits, techniques to deal with variations logic circuits are presented in Sect. 2.7.

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  1. Qualcomm Incorporated, 5775 Morehouse Drive, SanDiego, CA, 92131, USA

    Mohamed H. Abu-Rahma

  2. Electronics Engineering Department School of Sciences and Engineering, The American University in Cairo, AUC Avenue, New Cairo, 11835, Egypt

    Mohab Anis

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  1. Mohamed H. Abu-Rahma
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Abu-Rahma, M.H., Anis, M. (2013). Variability in Nanometer Technologies and Impact on SRAM. In: Nanometer Variation-Tolerant SRAM. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1749-1_2

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