Abstract
In this chapter, a novel digital calibration technique, called dynamic-mismatch mapping (DMM), is proposed to correct the non-linear effect caused by both amplitude and timing mismatch errors. The theoretical background of this proposed DMM is firstly explained. How to implement DMM in an easy and efficient way is discussed next. Matlab Monte-Carlo statistical simulations are also performed in this section to show the performance improvement by DMM, with a comparison to traditional static-mismatch mapping techniques. Finally, the application of DMM is discussed and summarized.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Q. Huang, P. Francese, C. Martelli, J. Nielsen, A 200 MS/s 14b 97 mW DAC in 0.18 μm CMOS, in Solid-State Circuits Conference, 2004. Digest of Technical Papers. ISSCC. 2004 IEEE International, vol. 1 (2004), pp. 364–532
W. Schofield, D. Mercer, L. Onge, A 16b 400 MS/s DAC with < -80 dBc IMD to 300 MHz and < -160 dBm/Hz noise power spectral density, in Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, vol. 1 (2003), pp. 126–482
Y. Cong, R. Geiger, A 1.5-V 14-bit 100-MS/s self-calibrated DAC. IEEE J. Solid-State Circ. 38(12), 2051–2060 (2003)
A. Bugeja, B.-S. Song, A self-trimming 14-b 100-MS/s CMOS DAC. IEEE J. Solid-State Circ. 35(12), 1841–1852 (2000)
G. Radulov, P. Quinn, H. Hegt, A. van Roermund, An on-chip self-calibration method for current mismatch in D/A converters, in Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European (2005), pp. 169–172
J. Hyde, T. Humes, C. Diorio, M. Thomas, M. Figueroa, A 300-MS/s 14-bit digital-to-analog converter in logic CMOS. IEEE J. Solid-State Circ. 38(5), 734–740 (2003)
C. Conroy, W. Lane, M. Moran, Statistical design techniques for D/A converters. IEEE J. Solid-State Circ. 24(4), 1118–1128 (1989)
G. Radulov, Flexible and self-calibrating current-steering digital-to-analog converters: analysis, classification and design, PhD Thesis, Eindhoven University of Technology, 2010
K. Rafeeque, V. Vasudevan, A new technique for on-chip error estimation and reconfiguration of current-steering digital-to-analog converters. IEEE Trans. Circ. Syst. I: Regular Papers 52(11), 2348–2357 (2005)
T. Chen, G. Gielen, The analysis and improvement of a current-steering DAC’s dynamic SFDR -II: the output-dependent delay differences. IEEE Trans. Circ. Syst. I: Regular Papers 54(2), 268–279 (2007)
T. Chen, G. Gielen, A 14-bit 200-MHz current-steering DAC with switching-sequence post-adjustment calibration. IEEE J. Solid-State Circ. 42(11), 2386–2394 (2007)
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2013 Springer Science+Business Media New York
About this chapter
Cite this chapter
Tang, Y., Hegt, H., van Roermund, A. (2013). A Novel Digital Calibration Technique: Dynamic-Mismatch Mapping (DMM). In: Dynamic-Mismatch Mapping for Digitally-Assisted DACs. Analog Circuits and Signal Processing, vol 92. Springer, New York, NY. https://doi.org/10.1007/978-1-4614-1250-2_5
Download citation
DOI: https://doi.org/10.1007/978-1-4614-1250-2_5
Published:
Publisher Name: Springer, New York, NY
Print ISBN: 978-1-4614-1249-6
Online ISBN: 978-1-4614-1250-2
eBook Packages: EngineeringEngineering (R0)