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A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement

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Emerging Memory Technologies

Abstract

In recent years, many systems have employed NAND flash memory as storage devices because of its advantages of high I/O performance, increasing capacity, and falling cost. On the other hand, the performance of NAND flash memory is limited by its “erase-before-write” requirement. Log-based structures have been used to alleviate this problem by writing updated data to the clean space. Log-based methods, however, cannot completely overcome the inherent limitation of NAND flash memory. It cannot avoid excessive erase operations when there are frequent updates, which quickly consume free pages, especially when some data are updated repeatedly. In this paper, we propose a hybrid architecture for the NAND flash memory storage, of which the log region is implemented using phase change random access memory (PCRAM). Compared to traditional log-based architectures, it has the following advantages: (1) the PCRAM log region allows in-place updating and byte-granularity access so that it significantly improves the usage efficiency of log pages by eliminating out-of-date log records; (2) it greatly reduces the traffic of reading from the NAND flash memory storage since the size of logs loaded for the read operation is decreased; (3) the energy consumption of the storage system is reduced as the overhead of writing and reading log data is decreased with the PCRAM log region; (4) the lifetime of NAND flash memory is increased because the number of erase operations are reduced. To facilitate the PCRAM log region, we propose several management policies. The simulation results show that our proposed methods can substantially improve the performance, energy consumption, and lifetime of the NAND flash memory storage.

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References

  1. Kgil, T., Roberts, D., & Mudge, T. (2008). Improving NAND flash based disk caches. In Proceedings of International Symposium on Computer Architecture (pp. 327–338). Doi: http://dx.doi.org/10.1109/ISCA.2008.32

  2. Tiwari, D., Vazhkudai, S.S., Kim, Y., Ma, X., Boboila, S., Desnoyers, P.J. (2012). Reducing data movement costs using energy efficient, active computation on ssd. In Proceedings of the 2012 USENIX conference on Power-Aware Computing and Systems, HotPower’12 (pp. 4–4). USENIX Association, Berkeley, CA, USA. http://dl.acm.org/citation.cfm?id=2387869.2387873

  3. Reinsel, D., & Janukowicz, J. (2008). White paper: Datacenter SSDs: Solid footing for growth. http://www.samsung.com/global/business/semiconductor/ products/flash/FlashApplicationNote.html

  4. Lee, S., Moon, B., Park, C., Kim, J., & Kim, S. (2008). A case for flash memory SSD in enterprise database applications. In Proceedings of ACM International Conference on Management of Data, (pp. 1075–1086). Doi: http://doi.acm.org/10.1145/1376616.1376723

  5. Lee, S., & Moon, B. (2007). Design of flash-based DBMS: An in-page logging approach. In Proceedings of ACM International Conference on Management of Data.

    Google Scholar 

  6. Lee, K., Kim, H., Woo, K., Chung, Y., & Kim, M. (2009). Design and implementation of MLC NAND flash-based DBMS for mobile devices. Journal of Systems and Software (March, 2009). Doi: http://doi.acm.org/10.1145/1289881.1289911

  7. Toshiba America Electronic Components, Inc.: NAND flash applications design guide (2004).

    Google Scholar 

  8. Leventhal, A. (2008). Flash storage memory. Journal of Communications of the ACM, 51(7), 47–51. Doi: http://doi.acm.org/10.1145/1364782.1364796

  9. Chiang, M., & Chang, R. (1999). Cleaning policies in mobile computers using flash memory. Journal of Systems and Software, 48(3), 213–231. Doi: http://dx.doi.org/10.1016/S0164-1212(99)00059-X

    Google Scholar 

  10. Rosenblum, M., & Ousterhout, J. (1992). The design and implementation of a log-structured file system. ACM Transaction on Computer Systems, 10(1), 26–52. Doi: http://doi.acm.org/10.1145/146941.146943

  11. Birrel, A., Isard, M., Thacker, C., & Wobber, T. (2005). A design for high-performance flash disks. Technical Report MSR-TR-2005-176, Microsoft Research.

    Google Scholar 

  12. Caulfield, A.M., Grupp, L.M., & Swanson, S. (2009). Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications. In Proceeding of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (pp. 217–228). Doi: http://doi.acm.org/10.1145/1508244.1508270

  13. Gupta, A., Kim, Y., & Urgaonkar, B. (2009). DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In Proceeding of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems, (pp. 229–240). Doi: http://doi.acm.org/10.1145/1508244.1508271

  14. Kim, S., & Jung, S. (2006). A log-based flash translation layer for large NAND flash memory. In Proceedings of International Conference on Advanced Communication Technology, 3, 1641–1644. doi:10.1109/ICACT.2006.206302.

  15. Sun, G., Dong, X., Xie, Y., Li, J., & Chen, Y. (2009). A novel architecture of the 3d stacked mram l2 cache for cmps. In High Performance Computer Architecture, 2009. HPCA 2009. 15th International Symposium on IEEE (pp. 239–249). doi: 10.1109/HPCA.2009.4798259.

    Google Scholar 

  16. Wu, X., Li, J., Zhang, L., Speight, E., Rajamony, R., & Xie, Y. (2009). Hybrid cache architecture with disparate memory technologies. In Proceedings of the 36th Annual International Symposium on Computer Architecture, ISCA ’09 (pp. 34–45). doi: 10.1145/1555754.1555761.

    Google Scholar 

  17. Dong, X., Wu, X., & Sun, G., et al. (2008). Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement. In DAC ’08: Proceedings of the 45th Annual Conference on Design Automation (pp. 554–559).

    Google Scholar 

  18. Zhang, W., & Li, T. (2009). Exploring phase change memory and 3D die-stacking for power/thermal friendly, fast and durable memory architectures. In International Conference on Parallel Architectures and Compilation Techniques.

    Google Scholar 

  19. Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2009). A durable and energy efficient main memory using phase change memory technology. In Proceedings of ISCA (pp. 14–23).

    Google Scholar 

  20. Lee, B.C., Ipek, E., Mutlu, O., & Burger, D. (2009). Architecting phase change memory as a scalable DRAM alternative. In Proceedings of ISCA (pp. 2–13).

    Google Scholar 

  21. Qureshi, M.K., Srinivasan, V., & Rivers, J.A. (2009). Scalable high performance main memory system using phase-change memory technology. In Proceedings of ISCA (pp. 24–33).

    Google Scholar 

  22. Qureshi, M., Franceschini, M., & Lastras-Montano, L., (2010). Improving read performance of phase change memories via write cancellation and write pausing. In High Performance Computer Architecture (HPCA), (2010). IEEE 16th International. Symposium, ( pp. 1–11). doi:10.1109/HPCA.2010.5416645.

  23. Qureshi, M.K., Karidis, J., Franceschini, M., Srinivasan, V., Lastras, L., & Abali, B. (2009). Enhancing lifetime and security of pcm-based main memory with start-gap wear leveling. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42 (pp. 14–23). ACM, New York, NY, USA. doi:10.1145/1669112.1669117.

  24. Zhou, P., Zhao, B., Yang, J., & Zhang, Y. (2009). A durable and energy efficient main memory using phase change memory technology. In Proceedings of the 36th annual international symposium on Computer architecture, ISCA ’09 (pp. 14–23). doi:10.1145/1555754.1555759.

  25. Seong, N.H., Woo, D.H., & Lee, H.H.S. (2010). Security refresh: prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping. In Proceedings of the 37th annual international symposium on Computer architecture, ISCA ’10 (pp. 383–394). ACM, New York, NY, USA. doi:10.1145/1815961.1816014.

  26. Park, Y., Lim, S., Lee, C., & Park, K. (2008). PFFS: a scalable flash memory file system for the hybrid architecture of phase-change RAM and NAND flash. In Proceedings of ACM Symposium on Applied Computing.

    Google Scholar 

  27. Kim, J., Lee, H., Choi, S., & Bahng, K. (2008). A PRAM and NAND flash hybrid architecture for high-performance embedded storage subsystems. In Proceedings of ACM International conference on Embedded software (pp. 31–40). Doi: http://doi.acm.org/10.1145/1450058.1450064

  28. Lam, C. (2008). Cell design considerations for phase change memory as a universal memory. In Proceedings of International Symposium on VLSI Technology, Systems and Applications (pp. 132–133). doi:10.1109/VTSA.2008.4530832.

  29. Lee, K., et al. (2007). A 90nm 1.8V 512Mb diode-switch PRAM with 266MB/s read throughput. In Proceedings of IEEE International Solid-State Circuits Conference (pp. 472–616). doi:10.1109/ISSCC.2007.373499.

  30. Lee, B.C., Ipek, E., Mutlu, O., & Burger, D. (2009). Architecting phase change memory as a scalable dram alternative. SIGARCH Computer Architecture News, 37(3), 2–13. doi:10.1145/1555815.1555758.

    Google Scholar 

  31. Cho, S., & Lee, H. (2009). Flip-n-write: a simple deterministic technique to improve pram write performance, energy and endurance. In Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 42 (pp. 347–357). ACM, New York, NY, USA. doi:10.1145/1669112.1669157.

  32. Caulfield, A.M., De, A., Coburn, J., Mollow, T.I., Gupta, R.K., & Swanson, S. (2010). Moneta: A high-performance storage array architecture for next-generation, non-volatile memories. In Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO ’43 (pp. 385–395). IEEE Computer Society, Washington, DC, USA. doi:10.1109/MICRO.2010.33.

  33. Akel, A., Caulfield, A.M., Mollov, T.I., Gupta, R.K., & Swanson, S. (2011). Onyx: a protoype phase change memory storage array. In Proceedings of the 3rd USENIX conference on Hot topics in storage and file systems, HotStorage’11 (pp. 2–2). USENIX Association, Berkeley, CA, USA http://dl.acm.org/citation.cfm?id=2002218.2002220

  34. Venkataraman, S., Tolia, N., Ranganathan, P., & Campbell, R.H. (2011). Consistent and durable data structures for non-volatile byte-addressable memory. In Proceedings of the 9th USENIX conference on File and storage technologies, FAST’11 (pp. 5–5). USENIX Association, Berkeley, CA, USA. http://dl.acm.org/citation.cfm?id=1960475.1960480

  35. Kang, D., Ahn, D., Kim, K., Webb, J., & Yi, K. (2003). One-dimensional heat conduction model for an electrical phase change random access memory device with an \(8f^{2}\) memory cell (f=0.15 \(\mu \)m). Journal of Applied Physics, 94, 3536–3542. doi:10.1063/1.1598272.

    Google Scholar 

  36. Hudgens, S. (2006). OUM nonvolatile semiconductor memory technology overview. In Proceedings of Materials Research Society Symposium.

    Google Scholar 

  37. Zhang, Y., et al. (2007). An integrated phase change memory cell with Ge nanowire diode for cross-point memory. In Proceedings of IEEE Symposium on VLSI Technology (pp. 98–99). doi:10.1109/VLSIT.2007.4339742.

  38. Park, S., Jung, D., Kang, J., Kim, J., & Lee, J. (2006). CFLRU: a replacement algorithm for flash memory. Architecture and Synthesis for Embedded Systems: In Proceedings of International Conference on Compilers (pp. 234–241).

    Google Scholar 

  39. Samsung Electronics: datasheet K9G8G08UOM (2006).

    Google Scholar 

  40. Samsung Electronics: datasheet KPS1215EZM (2006).

    Google Scholar 

  41. Nirschl, T., et al. (2007). Write strategies for 2 and 4-bit multi-level phase-change memory. In Proceedings of IEEE International Electron Devices Meeting (pp. 461–464). doi:10.1109/IEDM.2007.4418973.

  42. http://www.tpc.org

  43. Increasing flash solid state disk reliability. Technical Report, SiliconSystems (2005).

    Google Scholar 

  44. Chang, Y., Hsieh, J., & Kuo, T. (2007). Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design. In Proceedings of Design Automation Conference (pp. 212–217). Doi: http://doi.acm.org/10.1145/1278480.1278533

  45. Jung, D., Chae, Y., Jo, H., Kim, J., & Lee, J. (2007). A group-based wear-leveling algorithm for large-capacity flash memory storage systems. In Proceedings of International Conference on Compilers, Architecture and Synthesis for Embedded Systems (pp. 160–164). doi: http://doi.acm.org/10.1145/1289881.1289911

  46. http://hammerora.sourceforge.net/

  47. Shibata, N., et al. (2007). A 70 nm 16GB 16-Level-Cell NAND flash memory. Proceedings of IEEE Symposium on VLSI Circuits, 43(4), 929–937. doi:10.1109/JSSC.2008.917559.

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Authors and Affiliations

  1. Peking University, Beijing, China

    Guangyu Sun

  2. Ewha Womans University, Seoul, South Korea

    Yongsoo Joo

  3. Google Inc., Mountain View, CA, USA

    Yibo Chen

  4. University of Pittsburgh, Pittsburgh, USA

    Yuan Xie

  5. Pennsylvania State University, Pennsylvania, USA

    Yiran Chen

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  1. Guangyu Sun
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  2. Yongsoo Joo
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  3. Yibo Chen
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  4. Yiran Chen
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  5. Yuan Xie
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Correspondence to Yuan Xie .

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Editors and Affiliations

  1. Pennsylvania State University, University Park, Pennsylvania, USA

    Yuan Xie

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Sun, G., Joo, Y., Chen, Y., Chen, Y., Xie, Y. (2014). A Hybrid Solid-State Storage Architecture for the Performance, Energy Consumption, and Lifetime Improvement. In: Xie, Y. (eds) Emerging Memory Technologies. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9551-3_3

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  • DOI: https://doi.org/10.1007/978-1-4419-9551-3_3

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