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A Circuit-Architecture Co-optimization Framework for Exploring Nonvolatile Memory Hierarchies

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Emerging Memory Technologies

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Abstract

Many new memory technologies are available in building future energy-efficient memory hierarchies. It is necessary to have a framework that can quickly find the optimal memory technology on each hierarchy level. In this work, we first build a circuit-architecture joint design space exploration framework by combining RC circuit analysis and ANN-based performance modeling. Then, we use this framework to evaluate some emerging nonvolatile memory hierarchies. We demonstrate that an ReRAM-based cache hierarchy on an 8-core CMP system can achieve a 28 % EDP (Energy-Delay Product) improvement and a 39 % EDAP (Energy-Delay-Area Product) improvement compared to a conventional hierarchy with SRAM on-chip caches and DRAM main memory.

Extension of Conference Paper: This submission is extended from “A Circuit-Architecture Co-optimization Framework for Evaluating Emerging Memory Hierarchies” published on ISPASS’13. The additional material provided in the submission includes a detailed explanation of the circuit-level and the architecture-level models, a new case study of using PCRAM, and a sensitivity study on processor core counts. This work is supported in part by SRC grants, NSF 1218867, 1213052, 0903432 and by DoE under Award Number DE-SC0005026.

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Notes

  1. 1.

    Also called PCM or PRAM.

  2. 2.

    Also called STT-MRAM or MRAM.

  3. 3.

    Also called RRAM, CBRAM, or memristor.

  4. 4.

    Silicon area is the main factor that determines chip cost.

  5. 5.

    We also use the same methodology to collect the data for a 4-core CMP performance model, and the result is shown in Sect. 10.6.4.

  6. 6.

    Another 23 ANN models are built for the 4-core CMP model.

  7. 7.

    There are other models explaining the ReRAM working mechanism.

  8. 8.

    In this work, a neighboring option is generated by changing two parameters from the parameter set of L1 capacity, L1 associativity, L1 memory type, L2 capacity, L2 associativity, L2 memory type, L3 capacity, L3 associativity, and L3 memory type.

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Author information

Authors and Affiliations

  1. Qualcomm Technology, Inc., Qualcomm, USA

    Xiangyu Dong

  2. Google Inc., CA, USA

    Norman P. Jouppi

  3. Pennsylvania State University and AMD Research, Pennsylvania, USA

    Yuan Xie

Authors
  1. Xiangyu Dong
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  2. Norman P. Jouppi
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  3. Yuan Xie
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Correspondence to Yuan Xie .

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Editors and Affiliations

  1. Pennsylvania State University, University Park, Pennsylvania, USA

    Yuan Xie

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Dong, X., Jouppi, N.P., Xie, Y. (2014). A Circuit-Architecture Co-optimization Framework for Exploring Nonvolatile Memory Hierarchies. In: Xie, Y. (eds) Emerging Memory Technologies. Springer, New York, NY. https://doi.org/10.1007/978-1-4419-9551-3_10

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  • DOI: https://doi.org/10.1007/978-1-4419-9551-3_10

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