Abstract
This contribution presents an approach to mixed-level modeling using configurable MOS transistor models as part of a behavioral model. All effects of the complete MOS transistor model can be specifically enabled or disabled in the configurable model. By activating only the effects required for the behavioral model, simulation times can be reduced significantly with very little effort. The new method is demonstrated by partitioning the MOS level-1 transistor model according to effects and implementing a configurable MOS level-1 transistor model in Verilog-A. Several examples of use will show the reduction in simulation time. The proposed approach can be used with any type of transistor model and is easily integrated in circuit simulators such as SPICE.
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© 2008 Springer Science + Business Media B.V
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Weber, J., Lemke, A., Lehmler, A., Anton, M., Huss, S.A. (2008). Mixed-Level Modeling Using Configurable MOS Transistor Models. In: Villar, E. (eds) Embedded Systems Specification and Design Languages. Lecture Notes in Electrical Engineering, vol 10. Springer, Dordrecht. https://doi.org/10.1007/978-1-4020-8297-9_10
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DOI: https://doi.org/10.1007/978-1-4020-8297-9_10
Publisher Name: Springer, Dordrecht
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