Abstract
The variable block size motion estimation (VBSME) presented in the video coding standard H.264/AVC significantly improves coding efficiency, but it requires much more considerable computational complexity than motion estimation using fixed macroblocks. To solve this problem, this paper proposes a pipelined hardware architecture for full-search VBSME aiming for high performance, simple structure, and small controls. Our architecture consists of 1-D arrays with 64 processing elements, an adder tree to produce motion vectors (MVs) for variable block sizes, and comparators to determine the minimum of MVs. This can produce all 41 MVs for variable blocks of one macroblock in the same clock cycles to other conventional 1-D arrays of 64 PEs. In addition, this can be easily controlled by a 2-bit counter. Implementation results show that our architecture can estimate MVs in CIF video sequence at a rate of 106 frames/s for the 32×32 search range.
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References
ISO/IEC 14496-10: Coding of Moving Pictures and Audio (2002)
Zhang, J., He, Y., Yang, S., Zhong, Y.: Performance and Complexity Joint Optimization for H.264 Video Coding. In: Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, pp. 888–891 (2003)
Yap, S.Y., McCanny, J.V.: A VLSI Architecture for Variable Block Size Video Motion Estimation. IEEE Transactions on Circuits and Systems II: Express Briefs 51(7), 384–389 (2004)
Huang, Y.W., Wang, T.C., Hsieh, B.Y., Chen, L.G.: Hardware Architecture Design for Variable Block Size Motion Estimation in MPEG-4 AVC/JVT/ITU-T H.264. In: Proceedings of the 2003 International Symposium on Circuits and Systems, vol. 2, pp. 796–799 (2003)
Kao, C.Y., Lin, Y.L.: An AMBA-Compliant Motion Estimator for H.264 Advanced Video Coding. In: Proceedings of 2004 International Conference on SoC Design, vol. 1, pp. 117–120 (2004)
Wei, C., Gang, M.Z.: A Novel SAD Computing Hardware Architecture for Variable-size Block Motion Estimation and Its implementation. In: Proceedings of 5th International Conference on ASIC, vol. 2, pp. 950–953 (2003)
Kuhn, P.: Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation, pp. 18–19. Kluwer Academic Publishers, U.S.A (2003)
Richardson, I.E.G.: H.264 and MPEG-4 Video Compression, pp. 170–172. Wiley, UK (2004)
Shen, J.F., Wang, T.C., Chen, L.G.: A Novel Low-Power Full-Search Block-Matching Motion-Estimation Design for H.263+. IEEE Transactions on Circuits and Systems for Video Technology 11(7) (2001)
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Lee, SJ., Kim, CG., Kim, SD. (2005). A Pipelined Hardware Architecture for Motion Estimation of H.264/AVC. In: Srikanthan, T., Xue, J., Chang, CH. (eds) Advances in Computer Systems Architecture. ACSAC 2005. Lecture Notes in Computer Science, vol 3740. Springer, Berlin, Heidelberg. https://doi.org/10.1007/11572961_8
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DOI: https://doi.org/10.1007/11572961_8
Publisher Name: Springer, Berlin, Heidelberg
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