Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms

1. Front Matter

   Pages i-xiv

   PDF

2. Introduction

   Pages 1-7

3. Embedded SOC applications

   Pages 9-14

4. Classification of platform elements

   Pages 15-32

5. System level design principles

   Pages 33-42

6. Related work

   Pages 43-58

7. Methodology overview

   Pages 59-77

8. Unified timing model

   Pages 79-112

9. MP-SOC simulation framework

   Pages 113-139

10. Case study

    Pages 141-152

11. Summary

    Pages 153-157

12. Back Matter

    Pages 159-199

    PDF

We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytooptimallyutilizethepreciousresourcebandwidth. The computational power cannot be provided by traditional processor architectures and shared bus type of interconnects. The simple reason for this fact is energy ef?ciency: there exist orders of magnitude between the energy ef?ciency of an algorithm implemented as a ?xed functionality computational element and of a software implementation on a processor.

• Augmented Reality
• Electronic System Level (ESL)
• Multi-Processor System-on-Chip (MP-SoC)
• Network-on-Chip (NoC)
• Performance
• Processing
• QoS
• Simulation
• SystemC
• Transaction Level Modeling (TLM)
• architecture
• model
• modeling
• organization
• system on chip (SoC)

From the reviews:

"The book covers most of the major areas of system-level design and modeling, and much of the work described has been incorporated into a commercial ESL tool … . This book’s scope and range of pragmatic ideas make it valuable for a wide audience. … When combined with the extensive list of references (260!), this is a very valuable resource for anyone interested in the area … . It should resonate with students, researchers, and practical designers … ." (Grant Martin, IEEE Design and Test of Computers, May-June, 2007)

• CoWare, Germany

  Tim Kogel

• RWTH, Germany

  Rainer Leupers, Heinrich Meyr

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