3.7 Summary
This chapter covered symbolic simulation, its evolution and the baseline algorithm of reference. We also covered other related symbolic techniques and drew the analogy to simulation. Finally the last part of the chapter was dedicated to discuss some of the ongoing research in this area.
The next chapter will take a step back from the verification problem, and focus on introducing parametrizations and disjoint-support decompositions. Both these theoretical aspects will be deployed in the symbolic simulation solutions presented later in this book.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Mark D. Aagaard, Robert B. Jones, and Carl-Johan H. Seger. Formal verification using parametric representations of Boolean constraints. In DAC, Proceedings of Design Automation Conference, pages 402–407, June 1999.
Randal E. Bryant, Derek Beatty, Karl Brace, Kyeongsoon Cho, and Thomas Sheffler. COSMOS: A compiled simulator for MOS circuits. In DAC, Proceedings of Design Automation Conference, pages 9–16, June 1987.
Derek L. Beatty, Randall E. Bryant, and Carl-Johann H. Seger. Synchronous circuit verification by symbolic simulation: An illustration. In Proceedings of Sixth MIT Conference on Advanced Research in VLSI, pages 98–112, 1990.
Valeria Bertacco, Maurizio Damiani, and Stefano Quer. Cycle-based symbolic simulation of gate-level synchronous circuits. In DAC, Proceedings of Design Automation Conference, pages 391–396, June 1999.
Soumitra Bose and Allan Fisher. Verifying pipelined hardware using symbolic logic simulation. In ICCD, Proceedings of the International Conference on Computer Design, pages 217–221, October 1989.
Valeria Bertacco and Kunle Olukotun. Efficient state representation for symbolic simulation. In DAC, Proceedings of Design Automation Conference, June 2002.
Randall E. Bryant. Symbolic verification of MOS circuits. In Proceedings of 1985 Chapel Hill Conference on VLSI, pages 419–438, May 1985.
Olivier Coudert, Christian Berthet, and Jean Christophe Madre. Verification of synchronous sequential machines based on symbolic execution. In Automatic Verification Methods for Finite State Systems, International Workshop, volume 407 of Lecture Notes in Computer Science, pages 365–3. Springer, June 1989.
Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, and Stefano Quer. Disjunctive partitioning and partial iterative squaring: an effective approach for symbolic traversal of large circuits. In DAC, Proceedings of Design Automation Conference, pages 728–733, June 1997.
Gianpiero Cabodi, Paolo Camurati, and Stefano Quer. Improved reachability analysis of large finite state machine. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 354–360, November 1996.
William C. Carter, William H. Joyner, and Daniel Brand. Symbolic simulation for correct machine design. In DAC, Proceedings of Design Automation Conference, pages 280–286, June 1979.
Amit Goel and Randal E. Bryant. Set manipulation with Boolean functional vectors for symbolic reachability analysis. In DATE, Design, Automation and Test in Europe Conference, pages 10816–10821, March 2003.
Pei-Hsin Ho, Thomas Shiple, Kevin Harer, James Kukula, Robert Damiano, Valeria Bertacco, Jerry Taylor, and Jiang Long. Smart simulation using collaborative formal and simulation engines. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 120–126, November 2000.
James C. King. Symbolic execution and program testing. Communications of the ACM, 19(7):385–394, July 1976.
Alferd Kolbl, James Kukula, and Robert Damiano. Symbolic RTL simulation. In DAC, Proceedings of Design Automation Conference, pages 47–52, June 2001.
In-Ho Moon, James Kukula, Kavita Ravi, and Fabio Somenzi. To split or to conjoin: The question in image computation. In DAC, Proceedings of Design Automation Conference, pages 23–28, June 2000.
Gerd Ritter, Hans Eveking, and Holger Hinrichsen. Formal verification of designs with complex control by symbolic simulation. In CHARME, Proceedings of Advanced Research Working Conference on Correct Hardware Design and Verification Methods, pages 234–249. Springer-Verlag, 1999.
Kavita Ravi and Fabio Somenzi. High density reachability analysis. In ICCAD, Proceedings of the International Conference on Computer Aided Design, pages 154–158, November 1995.
Carl-Johan H. Seger and Randal E. Bryant. Formal verification by symbolic evaluation of partially-ordered trajectories. Formal Methods in System Design, 6(2): 147–189, 1995.
Miroslav N. Velev, Randal E. Bryant, and Alok Jain. Efficient modeling of memory arrays in symbolic simulation. In CAV, Proceedings of International Conference on Computer Aided Verification, volume 1254 of Lecture Notes in Computer Science, pages 388–399. Springer-Verlag, June 1997.
Dong Wang, Edmund Clarke, Yunshan Zhu, and Jim Kukula. Using cutwidth to improve symbolic simulation and Boolean satisfiability. In HLDVT, IEEE International High Level Design Validation and Test Workshop, pages 165–170, November 2001.
Chris Wilson and David L. Dill. Reliable verification using symbolic simulation with scalar values. In DAC, Proceedings of Design Automation Conference, pages 124–129, June 2000.
Jin Yang and Carl-Johan H. Seger. Introduction to generalized symbolic trajectory evaluation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(3):345–353, 2003.
Rights and permissions
Copyright information
© 2006 Springer Science+Business Media, Inc.
About this chapter
Cite this chapter
(2006). Symbolic Simulation. In: Scalable Hardware Verification with Symbolic Simulation. Springer, Boston, MA. https://doi.org/10.1007/0-387-29906-8_3
Download citation
DOI: https://doi.org/10.1007/0-387-29906-8_3
Publisher Name: Springer, Boston, MA
Print ISBN: 978-0-387-24411-2
Online ISBN: 978-0-387-29906-8
eBook Packages: EngineeringEngineering (R0)