Abstract
This chapter introduces how to design the target module on an FPGA from designers’ point of view. Now, FPGA vendors support integrated design tools which include all steps of design. Here, mainly Xilinx is adopted as an example, and its design flow is introduced from HDL description to programming and debugging devices. Next, high-level synthesis (HLS) which enables to design hardware with high-level programming language is introduced. In order to describe hardware, there are several restrictions and extension in front-end programming languages. The key issue to achieve enough performance is inserting pragmas for parallel processing and pipelining. Then, IP-based design for improving the productivity is introduced. The last subject of this chapter is how to use hard-macro processor in recent SoC-style FPGAs. Designers have to read a large amount of documents from vendors when they start the FPGA design, but by reading this chapter, they can get a brief overview of the total design.
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Izumi, T., Mitsuyama, Y. (2018). Design Flow and Design Tools. In: Amano, H. (eds) Principles and Structures of FPGAs. Springer, Singapore. https://doi.org/10.1007/978-981-13-0824-6_4
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DOI: https://doi.org/10.1007/978-981-13-0824-6_4
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