Performance Evaluation of 14-nm FinFET-Based Ring Counter Using BSIM-CMG Model

Abstract

Digital circuits are the heart of any modern microprocessor or microcontroller. Because of the vast advantages over analog integrated circuits, digital circuits are superior in terms of speed, performance and power consumption. Nowadays, digital designs are made up using semiconductor elements like MOSFET. This provides high-speed performance. Since the last 40 years, integrated circuits have been improving as per the Moore’s law. Reduction in size of transistors introduces several problems such as SCE and DIBL. One of the possible solution is FinFET which can mitigate the problems. Using FinFET and its different topologies, positive edge-triggered D flip-flop-based ring counter is examined at 14 nm technology. Simulation is done using HSPICE and BSIM-CMG FinFET model. By changing gate geometry and substrate, results are carried out. From the results, we can conclude that quadruple gate is better option in terms of delay, average power and current compare to tri-gate and double gate FinFET.