Abstract
Due to plenty of intrinsic overheads in synchronous circuit design, asynchronous designs have drawn consideration in the Electronic Design Automation Industry. In an asynchronous logic design methodologies, Null Convention Logic is the best delay-insensitive logic as it has many advantages such as inherent robustness, power consumption, and modular reusability. For digital signal processing and computational dynamic range applications, floating point multiplication is a critical part with high precision and low power. Null cycle reduction technique and fine grain pipelining can be applied to the Null Convention Logic floating point multiplier to increase throughput. In this paper, Multiplier using Asynchronous Delay-Insensitive single precision NCL Floating Point Multiplier with IEEE-754 standard architecture is proposed and its performance is compared with different topologies in terms of various metrics such as delay, area, power consumption, and percentage of energy savings.
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Sudhakar, J., Alekhya, Y., Syamala, K.S. (2018). A Dual-Rail Delay-Insensitive IEEE-754 Single-Precision Null Convention Floating Point Multiplier for Low-Power Applications. In: Saini, H., Singh, R., Reddy, K. (eds) Innovations in Electronics and Communication Engineering . Lecture Notes in Networks and Systems, vol 7. Springer, Singapore. https://doi.org/10.1007/978-981-10-3812-9_13
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DOI: https://doi.org/10.1007/978-981-10-3812-9_13
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