Abstract
This paper presents a low power comparator using Multi Threshold Super Cut-off Stack (MTSCStack) and Dual Threshold Transistor Stacking (DTTS) techniques using a 130 nm CMOS process technology. MTSCStack is proposed in order to decrease the leakage power in active mode and retaining the logic state of the comparator during the idle state. On the other hand, DTSS is proposed to decrease the leakage current with less impact on the delay. Based on the results, the total power consumption especially dynamic power has been reduced significantly by decreasing the VDD of the comparator. The static power and dynamic power of the post-layout proposed comparator is 797 pW and 17.55 µW respectively with delay of 1.08 ns.
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References
Osman NF (2014) A study on power reduction techniques for comparator based on body biasing. Master Thesis, Universiti Sains Malaysia
Panchal SD, Gajre SS, Ghanwat VP (2012) Design and implementation of 4-bit flash ADC using folding technique in cadence tool. Int J Adv Res Comput Commun Eng 1(4):238–241
Karimi G, Alimoradi A (2010) MTSCStack: an effective technique to decrease leakage power in VLSI circuits. In: International conference on electronic devices, system and application, pp 116–120
Aswale PS, Chopade SS (2013) Comparative study of different low power design techniques for reduction of leakage power in CMOS VLSI circuits. Int J Comput Appl 70(11):16–24
Rai A, Venkatesan BA (2014) Analysis and design of high speed low power comparator in ADC. Int J Eng Dev Res 2(1):103–109
Mohab A, Shawki A, Mohamed E (2003) Design and optimization of multithreshold CMOS (MTCMOS) circuits. IEEE Trans Comput Aided Des Integr Circuits Syst 22(10):1324–1342
Acknowledgment
Authors would like to thank Collaborative Microelectronic Design Excellence Centre (CEDEC) for supporting Cadence EDA tools software. Special acknowledgement to Universiti Sains Malaysia, ERGS grant no. 203/PELECT/6730112 for the funding of this work.
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Krishnan, P.M., Mustaffa, M.T. (2017). A Low Power Comparator Design for Analog-to-Digital Converter Using MTSCStack and DTTS Techniques. In: Ibrahim, H., Iqbal, S., Teoh, S., Mustaffa, M. (eds) 9th International Conference on Robotic, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 398. Springer, Singapore. https://doi.org/10.1007/978-981-10-1721-6_5
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DOI: https://doi.org/10.1007/978-981-10-1721-6_5
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