Development of At-speed Interconnect Test to Capture Marginal Open Defect on FPGA

Abstract

This paper highlights the development of FPGA interconnect at-speed test to capture marginal open defect on Altera® Stratix V devices. The need for at-speed test was due to the increasing number of marginal open defects, resulting from manufacturing process complexity anticipated on nanometer (nm) scale IC fabrication process. Towards the final implementation, there are few unique design implemented in order to generate the at-speed clocks and the pipelined scan enable signals to support Launch on Shift (LOS) method. Meanwhile, the ability to test the interconnect on at-speed frequency required new routing tool control variables to limit the interconnect path lengths and device power consumption. The LOS test patterns used in this research managed to cover up to 81 % of the overall routing resources for marginal open defect effectively. Furthermore, the test was successfully implemented at frequencies up to 400 MHz and proven to be sensitive to routing delay to capture marginal open defects.