Abstract
Pre-silicon verification process is important in an application having integrated chip design cycle. It is considered one of the biggest bottle-neck in modern day design projects. This paper intends to describe a testbench architecture that will improve verification efficiency and productivity for a Hard Memory Controller’s Sideband verification from the perspective of the test writer. The testbench architecture described by Universal Verification Methodology is reused, adapted and improved to allow higher level of automation within the testbench. The implemented autonomous agent is analyzed and compared against the regular agent for its efficiency in terms of lines of code need to be written by the test writer. The result obtained shows that the autonomous agent implemented in the architecture reduces the test writer’s burden by at least 60 % and up to 78 %.
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References
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Acknowledgments
The authors would like to thank Altera Corporations Sdn. Bhd and Universiti Sains Malaysia in supporting the carried out research investigation.
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Logeish Raj, R., Mohd-Mokhtar, R. (2017). Autonomous Agent for Universal Verification Methodology Testbench of Hard Memory Controller. In: Ibrahim, H., Iqbal, S., Teoh, S., Mustaffa, M. (eds) 9th International Conference on Robotic, Vision, Signal Processing and Power Applications. Lecture Notes in Electrical Engineering, vol 398. Springer, Singapore. https://doi.org/10.1007/978-981-10-1721-6_2
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DOI: https://doi.org/10.1007/978-981-10-1721-6_2
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Online ISBN: 978-981-10-1721-6
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