Abstract
SSD is made up by NAND Flash memories, DRAMs and a NAND controller. To realize a low-power high-speed SSD, the overall performance of the NAND Flash memory and the NAND controller should be optimized by co-designing both NAND and controller circuits. This chapter describes the most advanced circuits in this field.
Furthermore, 3D-integration in the SSD system becomes a key topic and an example of low power 3D-integrated SSD is shown.
Finally, a couple of techniques, Asymmetric Coding and Stripe Pattern Elimination Algorithm, for reducing the NAND raw BER are presented.
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References
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Takeuchi, K. (2013). NAND and Controller Co-design for SSDs. In: Inside Solid State Drives (SSDs). Springer Series in Advanced Microelectronics, vol 37. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-5146-0_7
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DOI: https://doi.org/10.1007/978-94-007-5146-0_7
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