Abstract
While networks-on-Chip (NoC) architectures may offer higher bandwidth compared to traditional bus-based communication, their performance can degrade significantly in the absence of effective flow control algorithms. This chapter presents a predictive closed-loop flow control mechanism, which is used to predict the congestion level in the network. Based on this information, the proposed scheme controls the packet injection rate at traffic sources in order to regulate the total number of packets in the network. Finally, simulations and experimental study using our FPGA prototype show that the proposed controller delivers a better performance compared to the traditional switch-to-switch flow control algorithms under various real and synthetic traffic patterns.
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Notes
- 1.
- 2.
A similar model for the output buffers can be also developed.
- 3.
Under the hotspot traffic, the nodes in the network receive packets with uniform probability, except a few (in our experiments 4) randomly selected nodes that receive some extra traffic.
- 4.
Note that the local memory in the host PE is not part of the router. The 100-flit local buffer is used to emphasize that (i) its size is finite and (ii) PEs sense the backpressure from the network for the switch-to-switch flow control.
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Ogras, U.Y., Marculescu, R. (2013). Analysis and Optimization of Prediction-Based Flow Control in Networks-on-Chip. In: Modeling, Analysis and Optimization of Network-on-Chip Communication Architectures. Lecture Notes in Electrical Engineering, vol 184. Springer, Dordrecht. https://doi.org/10.1007/978-94-007-3958-1_7
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