Abstract
This chapter summarizes the contributions of the techniques proposed in this book. To demonstrate the high performance of the WCC framework for an automatic WCET reduction, an overall evaluation of the developed optimization techniques is presented by applying these optimizations in sequence for a representative real-life benchmark. Finally, a discussion on directions for future work is provided.
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References
L. Almagor, K.D. Cooper, A. Grosul et al., Finding Effective Compilation Sequences, in Proceedings of the ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Washington, USA, June 2004, pp. 231–239
M. Wurst, K. Morik, Distributed feature extraction in a P2P setting—a case study. Future Gener. Comput. Syst. 23(1), 69–75 (2007). Special Issue on Data Mining
V. Zivojnović, J. Martínez Velarde, C. Schläger et al., DSPstone: a DSP-oriented benchmarking methodology, in Proceedings of the International Conference on Signal Processing and Technology (ICSPAT), Dallas, USA, January 1994, pp. 715–720
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© 2011 Springer Science+Business Media B.V.
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Lokuciejewski, P., Marwedel, P. (2011). Summary and Future Work. In: Worst-Case Execution Time Aware Compilation Techniques for Real-Time Systems. Embedded Systems. Springer, Dordrecht. https://doi.org/10.1007/978-90-481-9929-7_8
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DOI: https://doi.org/10.1007/978-90-481-9929-7_8
Publisher Name: Springer, Dordrecht
Print ISBN: 978-90-481-9928-0
Online ISBN: 978-90-481-9929-7
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