Reference Design of a Pulse-Based Receive Unit

The last section in this book provides a more technical discussion of the implementation details (and problems) of a fully integrated front-end of a pulse-based receive unit. In the full-scale implementation of the system, several of these modules would work together in parallel. They form the backbone of the pulse-based radio system which has been discussed throughout the previous chapters. The wideband receiver front end is intended for use in the 3.1 to 10.6 GHz band which was released by the fcc early in 2002 for use by so-called ultra-wideband (uwb) radio devices.

The receiver was implemented in a main-stream 0.18 μm standard cmos technology without any particular rf-enhancements. Incorporated in the 1.4 × 1.4 mm² chip are (1) a mixed-signal multiphase clock generator which concerts the interactions between different subsystems, (2) a mixer/pulse-to-baseband converter and (3) a baseband amplification chain. The dual in-phase/ quadrature (i/q) signal path of the receiver allows for coherent demodulation of phase modulated pulse-based radio signals. The design is optimized to cope with the large bandwidths at the rf-input stage and the baseband output buffers are able to directly drive an external analog-to-digital converter or measurement equipment. Three selectable sampling speeds are available in the receiver, supporting a maximum symbol rate of 107 Msymb/s. The entire system, which includes the clock drivers and the output buffers, consumes 120mW from a single 1.8 V power supply.