Sequential Design Guidelines

Abstract

This chapter describes about the key sequential design guidelines used in the ASIC design. These guidelines are essential for any ASIC design and used to improve the readability, performance, and need to be followed by an ASIC design engineer. The key guideline includes the use of nonblocking assignments in sequential designs, the use of synchronous resets and clock gating. The guidelines to use the pipelined stages in the design are described in detail and useful for improving the design performance. This chapter also covers the basic information about describing the Verilog RTL with multiple clocks, multiphase clocks and the issues with asynchronous resets.