Abstract
This chapter describes the complex combinational logic designs and covers the detail and practical oriented scenarios while describing the multiplexers, decoders, encoders, and priority encoders. The use of constructs like ‘‘if-else,’’ ‘‘case,’’ and continuous assignment ‘‘assign’’ are described in detail with the meaningful practical examples. The main focus of this chapter is to describe the design functionality with the synthesizable logic. Even this chapter focuses on the key practical issues need to be tackled while describing the Verilog HDL.
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© 2016 Springer India
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Taraate, V. (2016). Combinational Logic Design (Part II). In: Digital Logic Design Using Verilog. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2791-5_3
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DOI: https://doi.org/10.1007/978-81-322-2791-5_3
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Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2789-2
Online ISBN: 978-81-322-2791-5
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