Abstract
This chapter describes the use of Verilog HDL to code the combinational logic design and covers the small gate count designs. The chapter is organized in such a way that it can give the practical synthesizable Verilog HDL understanding with key practical scenarios and applications. The synthesizable Verilog HDL is described for the required functionality and the synthesized logic is explained for practical understanding. This chapter is useful to build the practical expertise to code the combinational designs using synthesizable Verilog constructs.
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© 2016 Springer India
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Taraate, V. (2016). Combinational Logic Design (Part I). In: Digital Logic Design Using Verilog. Springer, New Delhi. https://doi.org/10.1007/978-81-322-2791-5_2
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DOI: https://doi.org/10.1007/978-81-322-2791-5_2
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Publisher Name: Springer, New Delhi
Print ISBN: 978-81-322-2789-2
Online ISBN: 978-81-322-2791-5
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