Static Timing Analysis

Abstract

Static timing analysis (STA) is used for the timing checks for any ASIC designs. The objective of this chapter is to discuss in detail STA concepts used by the timing analyzer. This chapter discusses about the register timing parameters and their use in the frequency calculations. The positive clock skew and negative clock skew are also discussed in detail with the practical scenario. This chapter also focuses on the different timing paths and SDC commands and their use while writing the script. The solutions and techniques to fix the setup and hold violations are also discussed for the better understanding of the engineers. Even the timing exceptions like false and multicycle paths are covered with the practical scenario.