Multiple-Issue Processors

Abstract

Superscalar processors started to conquer the microprocessor market at the beginning of the 1990s with dual-issue processors. The principal motivation was to overcome the single issue of scalar RISC processors by providing the facility to fetch, decode, issue, execute, and write back results of more than one instruction per cycle. In fact, the first commercially successful super-scalar microprocessor was the Intel i960 RISC processor which hit the market in 1990. Further first-generation dual-issue superscalar RISC processors were the Motorola 88110, Alpha 21064, and the HP PA-7100.¹ Other super-scalar RISC processors of the mid-1990s era were the IBM POWER2 RISC System/6000 processor, its offspring PowerPC 601, 603, 604, 750 (G3), and 620, the DEC Alpha 21164, the Sun SuperSPARC and U1traSPARC, the HP PA-8000, and the MIPS R10000. Today’s superscalar RISC processors MIPS R12000, HP PA-8500, Sun U1traSPARC-II, IIi and III, Alpha 21264, IBM POWER2-Super-Chip (P2SC) are 4-issue or 6-issue processors.

What is the limitation of a multiple-issue approach? If we can issue five operations per clock cycle, why not 50? Limits on available instruction level parallelism are the simplest and most fundamental…

…What is clear is that some level of multiple issue is here to stay and will be included in all processors in the foreseeable future.

John L. Hennessy and David A. Patterson Computer Architecture A Quantitative Approach (Morgan Kaufmann Publishers, 1996)