Abstract
In this paper, we present a partial-parallel decoder architecture based on Min–Max algorithm for quasi-cyclic non-binary LDPC codes. An efficient architecture of the check node elementary processor is designed. The variable node update unit with fully parallel computation is proposed, which has the advantage of low complexity and latency by eliminating forward–backward operation and removing recursive computation among the message vector. Moreover, the FPGA simulation over GF(16) NB-LDPC is given to demonstrate the efficiency of the presented design scheme.
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Yang, L., Liu, F., Li, H. (2013). Min–Max Decoding for Non-Binary LDPC Codes. In: Lu, W., Cai, G., Liu, W., Xing, W. (eds) Proceedings of the 2012 International Conference on Information Technology and Software Engineering. Lecture Notes in Electrical Engineering, vol 210. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-34528-9_14
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DOI: https://doi.org/10.1007/978-3-642-34528-9_14
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Online ISBN: 978-3-642-34528-9
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