Abstract
The latency of network switching is of particular importance for fine-grained communication processes such as memory access. We propose a specialized network switch that reduces communication latency because many scientific computing applications have specific access patterns. In this paper, we describe the basic concept and design of our reconfigurable shared memory network. Our evaluation results show that there is no significant difference between the port-to-port latency of our network switch and that of an 8-port InfiniBand network switch. Furthermore, the hardware size of the routing stack in the network switch does not increase with the number of nodes.
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Ohnishi, Y., Yoshida, T. (2012). Design of an Application-Dependent Static-Based Shared Memory Network. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7440. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33065-0_7
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DOI: https://doi.org/10.1007/978-3-642-33065-0_7
Publisher Name: Springer, Berlin, Heidelberg
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