Abstract
In this paper, a new parallel phase algorithm for parallel turbo decoder is proposed. Traditional sliding window turbo algorithm exchanges extrinsic information phase by phase, it will induce long decoding latency. The proposed algorithm exchanges extrinsic information as soon as it had been calculated half the frame size, thus, it can not only eliminate (De-)Interleaver delay but also save the storage space. For verifying the proposed parallel phase turbo decoder, we have used FPGA to emulate the hardware architectures, and designed this turbo decoder chip with TSMC 0.18μm 1P6M CMOS process. The gate count of this decoder chip is 128284. The chip size including I/O pad is 1.91×1.91mm2. The simulation result shows that, compared to traditional sliding window method, for different code size, parallel phase turbo decoding method has 51.23%~58.13% decoding time saved, with 8 iteration times at 100MHz working frequency.
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References
3GPP specifications. 3rd generation partnership project (2000), http://www.3GPP.org/
DVB standards & bluebooks. Digital video broadcasting (2003), http://www.dvb.org/
Berrou, C., Glavieux, A., Thitimajshima, P.: Near Shannon limit error-correcting coding and decoding: Turbo codes. In: Proc. IEEE Int. Commun. Conf., pp. 1064–1070 (1993)
Robertson, P., Villebrun, E., Hoeher, P.: A comparison of optimal and suboptimal MAP decoding algorithms operating in the log domain. In: IEEE Int. Conf. on Commun., vol. 2, pp. 1009–1013 (1995)
Dawid, H., Meyr, H.: Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding. In: IEEE Int. Symp. on Personal, Indoor and Mobile Radio Commun., vol. 1, pp. 193–197 (1995)
Sun, Y., Zhu, Y., Goel, M., Cavallaro, J.R.: Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards. In: Proc. IEEE Int. Conf. Application-Specific Systems, Architectures and Processors, pp. 209–214 (July 2008)
Wang, L., Yang, H., Yang, H.: A novel method for parallel decoding of turbo codes. In: IEEE Int. Conf. Circuits and Systems for Communications, pp. 768–772 (2008)
Bahl, L.R., Cocke, J., Jelinek, F., Raviv, J.: Optimal Decoding of Linear Codes for Minimizing Symbol Error Rate. IEEE Trans. Inform. Theory 20, 284–287 (1974)
Viterbi, A.J.: An intuitive justification and a simplified implementation of the MAP decoder for convolutional codes. IEEE J. Select. Areas Commun. 16, 260–264 (1998)
Lee, W.T., Chang, Y.C.: Turbo decoder design employing a new phase estimation hard decision stopping criterion method. In: Proc. IEEE Int. Conf. Computer Science and Information Technology, pp. 237–240 (June 2011)
Boutillon, E., Gross, W.J., Gulak, P.G.: VLSI architectures for the MAP algorithm. IEEE Trans. Commun. 51(2), 175–185 (2003)
Lu, Y.C., Chen, T.C., Lu, E.H.: Low-latency turbo decoder design by concurrent decoding of component codes. In: IEEE Int. Conf. Innovative Computing Information and Control, pp. 533–536 (2008)
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Lee, WT., Chang, MS., Shen, WC. (2012). A New Low Latency Parallel Turbo Decoder Employing Parallel Phase Decoding Method. In: Xiang, Y., Stojmenovic, I., Apduhan, B.O., Wang, G., Nakano, K., Zomaya, A. (eds) Algorithms and Architectures for Parallel Processing. ICA3PP 2012. Lecture Notes in Computer Science, vol 7440. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-33065-0_14
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DOI: https://doi.org/10.1007/978-3-642-33065-0_14
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