Abstract
The design technique of using gray code addressing to reduce power dissipation in CPU of pacemaker is presented in this paper. The experimental results of reducing power up to 20% would be a promising result. This work is implemented by using Altera Quartus II 9.0, the device Cylone II EP2C20F484C7 is used.
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© 2013 IFMBE
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Khoa, L.T., Trang, H. (2013). Design an Optimized CPU Architecture for Pacemaker Applications. In: Toi, V., Toan, N., Dang Khoa, T., Lien Phuong, T. (eds) 4th International Conference on Biomedical Engineering in Vietnam. IFMBE Proceedings, vol 49. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-32183-2_14
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DOI: https://doi.org/10.1007/978-3-642-32183-2_14
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-32182-5
Online ISBN: 978-3-642-32183-2
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