Abstract
Behavioural equivalence checking of the refinements of the input behaviours taking place at various phases of synthesis of embedded systems or VLSI circuits is a well pursued field. Although extensive literature on equivalence checking of sequential behaviours exists, similar treatments for parallel behaviours are rare mainly because of all the possible execution scenarios inherent in them. Here, we propose a translation algorithm from a parallel behaviour, represented by an untimed PRES+ model, to a sequential behaviour, represented by an FSMD model. Several equivalence checkers for FSMD models already exist for various code based transformation techniques. We have satisfactorily performed equivalence checking of some high level synthesis benchmarks represented by untimed PRES+ models by first translating them into FSMD models using our algorithm and subsequently feeding them to one such FSMD equivalence checker.
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References
Edwards, S., Lavagno, L., Lee, E.A., Sangiovanni-Vincentelli, A.: Design of embedded systems: Formal models, validation, and synthesis. Proceedings of the IEEE, pp. 366–390 (1997)
Cortés, L.A., Eles, P., Peng, Z.: Verification of embedded systems using a petri net based representation. In: ISSS 2000: Proceedings of the 13th International Symposium on System Synthesis, pp. 149–155. IEEE Computer Society, Washington, DC (2000)
Gupta, S., Gupta, R., Dutt, N., Nicolau, A.: Coordinated parallelizing compiler optimizations and high-level synthesis. ACM Transactions on Design Automation of Electronic Systems (TODAES) 9(4), 1–31 (2004)
Dos Santos, L.C.V., Jress, J.A.G.: A reordering technique for efficient code motion. In: Procs. of the 36th ACM/IEEE Design Automation Conference, DAC 1999, pp. 296–299. ACM, New York (1999)
Lakshminarayana, G., Raghunathan, A., Jha, N.K.: Incorporating speculative execution into scheduling of control-flow-intensive design. IEEE Transactions on CAD of ICS 19(3), 308–324 (2000)
Wakabayashi, K., Tanaka, H.: Global scheduling independent of control dependencies based on condition vectors. In: DAC 1992: Proceedings of the 29th ACM/IEEE Conference on Design Automation, pp. 112–115 (1992)
Rim, M., Fann, Y., Jain, R.: Global scheduling with code motions for high-level synthesis applications. IEEE Transactions on VLSI Systems 3(3), 379–392 (1995)
Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Using global code motions to improve the quality of results for high-level synthesis. IEEE Transactions on CAD of ICS 23(2), 302–312 (2004)
Kandemir, M., Vijaykrishnan, N., Irwin, M.J., Ye, W.: Influence of compiler optimizations on system power. IEEE Trans. Very Large Scale Integr. Syst. 9, 801–804 (2001)
Kandemir, M., Son, S.W., Chen, G.: An evaluation of code and data optimizations in the context of disk power reduction. In: ISLPED 2005: Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 209–214 (2005)
Kandemir, M.T.: Reducing energy consumption of multiprocessor soc architectures by exploiting memory bank locality. ACM Trans. Des. Autom. Electron. Syst. 11(2), 410–441 (2006)
Radhakrishnan, R., Teica, E., Vemuri, R.: Verification of Basic Block Schedules Using RTL Transformations. In: Margaria, T., Melham, T.F. (eds.) CHARME 2001. LNCS, vol. 2144, pp. 173–178. Springer, Heidelberg (2001)
Eveking, H., Hinrichsen, H., Ritter, G.: Automatic verification of scheduling results in high-level synthesis. In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 1999, pp. 260–265. ACM, New York (1999)
Kim, Y., Kopuri, S., Mansouri, N.: Automated formal verification of scheduling process using finite state machines with datapath (fsmd). In: Proceedings of the 5th International Symposium on Quality Electronic Design, ISQED 2004, pp. 110–115. IEEE Computer Society, Washington, DC (2004)
Tristan, J.-B., Leroy, X.: Verified validation of lazy code motion. In: Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2009, pp. 316–326. ACM, New York (2009)
Kim, Y., Mansouri, N.: Automated formal verification of scheduling with speculative code motions. In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI, GLSVLSI 2008, pp. 95–100. ACM, New York (2008)
Kundu, S., Lerner, S., Gupta, R.: Validating High-Level Synthesis. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 459–472. Springer, Heidelberg (2008)
Karfa, C., Sarkar, D., Mandal, C., Reade, C.: Hand-in-hand verification of high-level synthesis. In: GLSVLSI 2007: Proceedings of the 17th ACM Great Lakes Symposium on VLSI, pp. 429–434. ACM, New York (2007)
Karfa, C., Sarkar, D., Mandal, C., Kumar, P.: An equivalence-checking method for scheduling verification in high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(3), 556–569 (2008)
Kim, Y., Kopuri, S., Mansouri, N.: Automated formal verification of scheduling process using finite state machines with datapath (fsmd). In: Proceedings of the 5th International Symposium on Quality Electronic Design, ISQED 2004, pp. 110–115. IEEE Computer Society, Washington, DC (2004)
Bandyopadhyay, S.: Equivalence checking in embedded systems design verification using pres+ model. CoRR, abs/1010.4953 (2010)
Panda, P.R., Dutt, N.D.: 1995 high level synthesis design repository. In: Proceedings of the 8th International Symposium on System Synthesis, ISSS 1995, pp. 170–174 (1995)
Gajski, D.D., Dutt, N.D., Wu, A.C.-H., Lin, S.Y.-L.: High-level synthesis: introduction to chip and system design. Kluwer Academic Publishers, Norwell (1992)
Gupta, S., Dutt, N., Gupta, R., Nicolau, A.: Spark: a high-level synthesis framework for applying parallelizing compiler transformations. In: Proc. of Int. Conf. on VLSI Design, pp. 461–466. IEEE Computer Society, Washington, DC (2003)
Alizadeh, B., Fujita, M.: Automatic Merge-Point Detection for Sequential Equivalence Checking of System-Level and RTL Descriptions. In: Namjoshi, K.S., Yoneda, T., Higashino, T., Okamura, Y. (eds.) ATVA 2007. LNCS, vol. 4762, pp. 129–144. Springer, Heidelberg (2007)
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Bandyopadhyay, S., Banerjee, K., Sarkar, D., Mandal, C.R. (2012). Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_9
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DOI: https://doi.org/10.1007/978-3-642-31494-0_9
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