Abstract
Multipliers which can support flexible input size are a crucial component of finite field processors. The present paper targets efficient VLSI design of such variable size multipliers, operating on characteristic 2 field polynomials with degree varying to 512 bits. In order to optimize the area, and speed the design employs a sequential architecture, utilizing the Karatsuba-Ofman decomposition. The architecture reduces the critical path by designing an overlap free variant of the original Karatsuba algorithm. Apart from exploring wrt. the design parameters, namely levels and thresholding for Karatsuba multipliers, the paper also observes the effect of combinations of overlap free and naive Karatsuba multipliers on the overall area and speed. The results show that on a standard Virtex-4 platform, two levels of overlap free Karatsuba multipliers provides better area-time product and lesser computation delay.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Fourth International Conference on Information Technology: New Generations (ITNG 2007), April 2-4, Las Vegas, Nevada, USA. IEEE Computer Society (2007)
Chow, G.C.T., Eguro, K., Luk, W., Leong, P.: A karatsuba-based montgomery multiplier. In: Proceedings of the 2010 International Conference on Field Programmable Logic and Applications, FPL 2010, pp. 434–437. IEEE Computer Society, Washington, DC (2010)
Fan, H., Sun, J., Gu, M., Lam, K.-Y.: Overlap-free karatsuba-ofman polynomial multiplication algorithms. IACR Cryptology ePrint Archive 2007:393 (2007)
Preneel, B., Tavares, S. (eds.): SAC 2005. LNCS, vol. 3897. Springer, Heidelberg (2006)
Rebeiro, C.: Architecture Explorations For Elliptic Curve Cryptography On FPGAs (February 2009)
Rebeiro, C., Mukhpodhyay, D.: Power attack resistant efficient fpga architecture for karatsuba multiplier. In: Proceedings of the 21st International Conference on VLSI Design, VLSID 2008, pp. 706–711. IEEE Computer Society, Washington, DC (2008)
Wajih, E.-H., Mohsen, M., Medien, Z., Belgacem, B.: Efficient hardware architecture of recursive karatsuba-ofman multiplier. In: 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, DTIS 2008, pp. 1–6 (March 2008)
Weimerskirch, A., Paar, C.: Generalizations of the Karatsuba Algorithm for Efficient Implementations. Cryptology ePrint Archive, Report 2006/224 (2006)
Zhou, G., Michalik, H., Hinsenkamp, L.: Complexity analysis and efficient implementations of bit parallel finite field multipliers based on karatsuba-ofman algorithm on fpgas. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18(7), 1057–1066 (2010)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2012 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Basu Roy, D., Mukhopadhyay, D. (2012). An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs. In: Rahaman, H., Chattopadhyay, S., Chattopadhyay, S. (eds) Progress in VLSI Design and Test. Lecture Notes in Computer Science, vol 7373. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-31494-0_12
Download citation
DOI: https://doi.org/10.1007/978-3-642-31494-0_12
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-31493-3
Online ISBN: 978-3-642-31494-0
eBook Packages: Computer ScienceComputer Science (R0)